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I am trying to build a circuit which converts 6V DC to 5V DC. I have simulated the circuit using multisim and have achieve a "fairly" stable output of 5V.

However, when I tried to measure the output voltage from the opamp (LM741) it oscillates around ~0.1mV to 9V (measured at probe5).

The datasheet for the IRF5305 says the gate threshold voltage is 2V to 4V,.

Is there anyway to stabilize the output voltage from my opamp to the MOSFET?

enter image description here

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    \$\begingroup\$ LM741 on 6V? I'm surprised it worked at all! (minimum recommended power supply voltage is 20V). \$\endgroup\$ Commented Nov 8, 2020 at 4:18
  • \$\begingroup\$ @BruceAbbott Hi, thanks for the comment, it seems like there is something wrong with my wiring. \$\endgroup\$
    – Axois
    Commented Nov 8, 2020 at 4:28
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    \$\begingroup\$ @Axois I still agree with Bruce. The LM741 is not appropriate. Actually, if you are bent on using IC amp I'd explore using a TL431 (for a 2.5 V ref voltage) and an LM393A with a PNP BJT. It's trivial to set up and it will just work right. Put the ref output voltage to the (-) input and use a resistor divider from the output voltage back to the (+) input. The PNP BJT will need a small pull-up resistor (the LM393A output is OC) -- depending on your load details. You may also need a small capacitor to stabilize, but I'd need more details to suggest one. (I also need accuracy details.) \$\endgroup\$
    – jonk
    Commented Nov 8, 2020 at 6:54
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    \$\begingroup\$ @Axois All this can also be done with discrete BJTs, as well. (With some loss of accuracy and repeatability.) But the LM393A is a nice device and has very general utility (including audio amplifiers, surprisingly.) So it may be better to learn how to use it with the TL431 (which also has very general utility.) \$\endgroup\$
    – jonk
    Commented Nov 8, 2020 at 7:03

4 Answers 4

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I made some comments, earlier. I figure I may as well add a specific schematic. (So that it can be criticized, as appropriate.)

schematic

simulate this circuit – Schematic created using CircuitLab

On the left side, the TL431 provides a \$2.5\:\text{V}\$ reference voltage.

I don't know your \$6\:\text{V}\$ rail details (is it unregulated, or not; what's its output impedance; etc) or your load requirements (how much current compliance; what's the dynamic range needed; etc), so the above circuit is just to be taken as a rough idea -- a little more than just a behavioral circuit but not actually designed for anything particular, either.

The LM393A is an OC output so \$R_3\$ is needed to pull up the output. \$R_4\$ and \$R_5\$ make up the obvious voltage divider that is compared with the TL431 output voltage. \$C_4\$ is a small output capacitance.

I've added \$R_8\$ to manage the bulk base resistance (make it known as opposed to unknown) of the PNP BJT. (\$R_8\$ also helps with high frequency oscillation.) I also included \$R_7\$ and just gave it some value. What it should do is drop about \$150\:\text{mV}\$ at the highest "normal" load current. As I've no idea what that is, I just picked something. (If you want, just short/remove \$R_7\$.)

Oscillation is a problem with PNP LDOs (or PFET.) So I added \$C_2\$ and \$R_6\$

Don't use the above, blindly. But it gets across one possible topology.

You can replace the LM393A (which is a pretty simple comparator -- kind of like a simplified opamp) and replace it with a rail-to-rail output (well, it has to reach close to the top rail anyway) opamp like the LT1800, for example. (But you'd pay a LOT more for that.) Also, you could replace the PNP BJT with a PFET, so long as you make sure the threshold voltage can achieved by the opamp's output. If you use a PFET, there's no need at all for \$R_7\$ so just jumper that. \$R_8\$ will still serve a small purpose, so leave it. So you have some options. And using a PFET might be important where your output current compliance is large and you want to keep the part count small.

The topology itself is generally versatile.

P.S. I haven't attempted to do much analysis here. It's just tossed out, so to speak, without a lot of examination. In general, I think it is in the vague ballpark of a modest regulator. But details matter. So it may require changes depending upon more details, as they arrive. It's just a concept here.

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The most obvious way would be to add a negative feedback path that has low impedance at high frequency.

To do this change the 10 ohm resistor to 100 ohms and then add a 100pF capacitor from the output of the op-amp to the negative input of the op-amp. If 100pF is insufficient you may try increasing it up to a few nF.

This will of course reduce the power supply rejection of the regulator at high frequency, but at least it should stabilize it.

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  • \$\begingroup\$ This stabilized the output of the opamp, but the voltage at the load fluctuated even more \$\endgroup\$
    – Axois
    Commented Nov 8, 2020 at 5:01
  • \$\begingroup\$ What kind of load are you driving? And how much capacitance do you have at the regulator output? I don't see any significant capacitance in your picture. \$\endgroup\$
    – user4574
    Commented Nov 8, 2020 at 5:14
  • \$\begingroup\$ I think your issue in general is that the op-amp can't drive the P-FET quick enough, which leads to phase lag and instability. The fix I suggested just puts in a separate feedback path to stabilize the op-amp. This approach does reduce the ability of the op-amp to adjust to sudden load changes. This problem can be compensated for by adding more capacitance on the output of the regulator. \$\endgroup\$
    – user4574
    Commented Nov 8, 2020 at 5:14
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For stabilization (assuming the UA741 is itself happy with only 6 volts on its VDD, you can insert a stabilization network

  • insert 10Kohm resistor in series with the wiper of the pot

  • add 1uF capacitor from output of the Pchannel to the Vin+ of the opamp

Presumably the ENTIRE LOOP is what is oscillating.

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  • \$\begingroup\$ did you mean the Vin- of the opamp for negative feedback? in my circuit i am feeding back to the positive terminal because i am using a Pmos \$\endgroup\$
    – Axois
    Commented Nov 8, 2020 at 4:49
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While jonk's answer was a more generic solution to building a PFet LDO, I have realised that the oscillation is caused by the ESR of the filter capacitors C4 and C3. Changing into a smaller resistor value of 100ohms results in greater stability of the output.

However, one can also stabilise the output by adding a capacitor to the output of the mosfet to increase the phase lag caused by the ESR.

enter image description here

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