I am somewhat confused by what should be the amplifier output voltage after a purely CM signal is fed. Let me it clarify what I'm talking about:
simulate this circuit – Schematic created using CircuitLab
I would say it should be \$0\$ because, assuming large DC CMRR, such 1V CM will be blasted off by the amplifier. Mathematically, since \$v_{out} = A_{diff}(v_{diff}+\frac{v_{CM}}{CMRR})\$.
However, I'm rather told one should expect a midrange output wrt supply rails, from a design standpoint. Thus, if say the amplifier is railed from +3V to 0V then I should expect \$V_{out}=1.5V\$. This criteria actually leads to some design specs at the output stage, where one should size the transistors to have exactly the same current.
This standpoint eventually results in the same conclusion if supply rails are symmetric e.g. from +3V to -3V, but then I wouldn't expect a Vout = 0V for +3V and 0V, as Circuitlab says.
So, which one is correct? Or are we talking about the same thing?
Clarifications are due, I'm sorry. I do know a real amplifier will inevitabily be affected by a statistical offset voltage, likely leading to saturation close to rails depending on polarity. But that's not the point of the question.
My question is: if theoretically \$\mathbf {V_{OS}=0}\$, then, for high CMRR, should one expect Vout to be slightly above 0V (i.e. regardless of the opamp supply rails) or should one expect it to be at mid range i.e. close to \$(Vcc-|Vss|)/2\$? From the previous \$v_{out}\$ equation, I would say the former -- but I wouldn't know whether the output stage may be able to reach it without a negative rail (if for instance the opamp was powered with +3V and ground on the lower side).