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I am somewhat confused by what should be the amplifier output voltage after a purely CM signal is fed. Let me it clarify what I'm talking about:

schematic

simulate this circuit – Schematic created using CircuitLab

I would say it should be \$0\$ because, assuming large DC CMRR, such 1V CM will be blasted off by the amplifier. Mathematically, since \$v_{out} = A_{diff}(v_{diff}+\frac{v_{CM}}{CMRR})\$.

However, I'm rather told one should expect a midrange output wrt supply rails, from a design standpoint. Thus, if say the amplifier is railed from +3V to 0V then I should expect \$V_{out}=1.5V\$. This criteria actually leads to some design specs at the output stage, where one should size the transistors to have exactly the same current.

This standpoint eventually results in the same conclusion if supply rails are symmetric e.g. from +3V to -3V, but then I wouldn't expect a Vout = 0V for +3V and 0V, as Circuitlab says.

So, which one is correct? Or are we talking about the same thing?


Clarifications are due, I'm sorry. I do know a real amplifier will inevitabily be affected by a statistical offset voltage, likely leading to saturation close to rails depending on polarity. But that's not the point of the question.

My question is: if theoretically \$\mathbf {V_{OS}=0}\$, then, for high CMRR, should one expect Vout to be slightly above 0V (i.e. regardless of the opamp supply rails) or should one expect it to be at mid range i.e. close to \$(Vcc-|Vss|)/2\$? From the previous \$v_{out}\$ equation, I would say the former -- but I wouldn't know whether the output stage may be able to reach it without a negative rail (if for instance the opamp was powered with +3V and ground on the lower side).

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  • \$\begingroup\$ (1V / CMRR + input offset voltage) * open loop gain. Bounded by teh supply rails. \$\endgroup\$ – user_1818839 Nov 8 '20 at 16:24
  • \$\begingroup\$ Theoretically: yes \$V_{out}\$ = 0, in the real world: see Brian's comment. Realize that in a simulator you could be simulating the theoretical situation. The next level of using a circuit simulator is knowing when you can trust its results and when you cannot (and this is one of those cases). So stop thinking that the simulator is always correct. \$\endgroup\$ – Bimpelrekkie Nov 8 '20 at 16:30
  • \$\begingroup\$ @Bimpelrekkie: Surely, but I wasn't saying that. If you take into account non-idealities such as finite Vos, bias currents etc. then definitely Vout will be above the ideal value by some mV (say). But my question is what should Vout be? Midrange wrt supplies or 0? Hope the question is clear, please say if not. \$\endgroup\$ – edmz Nov 8 '20 at 16:59
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    \$\begingroup\$ This is impossible to predict. You need to instead measure the gain error using a differential input with feedback, taking into account the effect of limited op-amp gain. \$\endgroup\$ – hacktastical Nov 8 '20 at 17:53
  • \$\begingroup\$ But my question is what should Vout be? See the first comment. Also realize that the input offset voltage varies per device. input offset voltage does not have one value. Maybe you're expecting one value like: Vout = 1 V. That's not what is happening here. Vout depends on chance, for many opamps Vout = voltage of positive supply - some value and for many most others it will be: Vout = voltage of negative supply + some value. \$\endgroup\$ – Bimpelrekkie Nov 8 '20 at 18:29
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With an open loop amplifier, with colossal gain, and finite but unknown input offsets, you should regard the output voltage as completely undefined.

If you take any real amplifier from your spares box and wire it up like that, it's more likely for the output to be saturated on one or other rail as it is to be in the linear region between them. That's what should be expected from a design standpoint.

With a simulated opamp, it depends what the model for the amplifier does. If it is is given precisely 0 V for the input offsets, and a very large CMRR, then you may get a mid rail output.

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