I was given the task to evaluate existing boundary scan systems. At this moment, we are using a simple solution which allows us to define boundary scan vectors which we can check. This is fine for simple tests and is perfectly integrated into our ICT/Flying Probe/AOI chain. For a new project we require testing of various high speed interfaces. We've been talking with Goepel about our requirements but I am not completely satisfied with the answers from their sales guys. I simply do not trust them (I think this is more my being than not believing the actual sales guys). When talking about more advanced microcontrollers (Cortex-A8/A9 core, ..) they said it was just a question of purchasing the appropriate model for the controller and an appropriate model for the DDR-RAM and it would be able to create the checks automatically. I believe that this holds true for interfaces which do not have the timing requirements and can be considered static (SRAM, various logic ICs, ...). I asked about DDR-RAM (actually it's gonna be DDR2 or DDR3) functionality and they said it should work, but on the other side the demonstrated a "simple" SRAM.
Now for my question: Has anyone of you made an experience with such high speed circuits in conjunction with boundary scan? I just want to avoid telling our customer "Yes, we can do this" when it's just all wrong. Furthermore: Using JTAG, we are definitely not able to achieve the timing requirements of DDR2/DDR3, this alone already seems like a problem to me. How do you do testing of such high speed interfaces (GBit Eth, various SERDES, DDR)? We've been thinking about functional testing, would this be the way to go?
EDIT: Additional Information due to response from Dave Tweed:
I am in fact targeting manufacturing flaws. In no way I expect components to work out of specs or to differ between production runs, this is out of scope. Also, timing is no concern to me. Basically I would just like to rule out any shorts or unconnects which may happen during production (this is especially hard with BGAs which cannot be checked using AOI).
To have DDR-RAM work as expected, I need to stay within timing restrictions. Due to the speed of the JTAG interface (and its nature) it's just not possible to to stay within the specified timing. The main question is now: Is there something I might have left out or forgotten which makes testing (e.g. DDR-RAM) very easy or is this something which can only be done by performing a functional test at a later stage?
I'll give an example: I have a controller which supports Boundary Scan on its DDR lines. BUT the memory itself does NOT. Therefore I have the following options: 1) Do a functional test (a la memtest in Linux); 2) Build a "kind of" memory access sequence via Boundary Scan (which will be out of specs) to test memory access (address and data lines, write some data to RAM, read it back).