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I am trying to figure out the stability of an amplifier, for which I have to calculate the loop gain and make sure its not negative for instability. In Cadence one can use 'stb' analysis to calculate loop gain. The loop gain and phase looks as follows enter image description here

The circuit:

enter image description here

With respect to the phase of the loop gain starting at -180 degrees, this has to do with a sign convention adopted by cadence. Please check these links if you are more interested https://sites.google.com/site/frankwiedmann/loopgain https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/30938/stb-analysis-phase-margin-gain-margin-functions/1338980#1338980

In this case the 0 dB gain is at roughly 9.2 MHz and the phase margin is negative 5 degrees, indicating unstable behavior. But if I try to calculate phase margin from direct plot form, I do not get a value of phase margin as shown below:

enter image description here

Can anyone throw light on this problem?

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    \$\begingroup\$ Your bodeplot will be easier to read if you use a logarithmic X-axis (for the frequency). You might have to re-do the simulation using a logarithmic frequency sweep to get a nice plot. Also show your circuit. loop gain starting at -180 degrees just look at the phase change compared to DC or a very low frequency because essentially, the phase change is what matters (assuming stability at DC). \$\endgroup\$ Nov 9 '20 at 14:57
  • \$\begingroup\$ What is the problem? The BODE plot gives a negative margin (-5 deg). What is the result of the stb analysis? A phase of -180deg for low frequencies (and DC) is correct because a DC stable operating point requires negative feedback. \$\endgroup\$
    – LvW
    Nov 9 '20 at 15:19
  • \$\begingroup\$ @Bimpelrekkie I added the circuit and changed the x-axis to logarithmic \$\endgroup\$
    – RAN
    Nov 9 '20 at 15:27
  • \$\begingroup\$ @LvW The Bode plot is actually the loop gain, which is the result of stb analysis. The problem is direct plot does not give me the phase margin as shown in the picture \$\endgroup\$
    – RAN
    Nov 9 '20 at 15:29
  • \$\begingroup\$ Plotting the loop gain is sometimes "problematic" You have to restore the correct DC operational point and the proper loading at the opening. And the (normal) input signal must be set to zero. I am afraid, your simulation setup is not correct. WHERE did you OPEN the loop? \$\endgroup\$
    – LvW
    Nov 9 '20 at 16:00
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The STB main form in Virtuoso will produce eval errors for any negative or gain phase margin, the same is true if you use the PhaseMargin function in the calculator. In cases such as these, doing it manually is sometimes the easiest way to see what is going on. Don't forget that ideally you want a phase margin of ~60, and general rule of thumb is > 45 to ensure stability.

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  • \$\begingroup\$ It may be of use to others to know that the iprobe should cut the loop entirely. In the circuit shown there may be an internal loop in the amplifier symbol. The only visible place that cuts the loop entirely is at the output of the amplifier symbol. \$\endgroup\$
    – HKOB
    Mar 11 at 19:39

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