3
\$\begingroup\$

The figure is taken from https://ece.uwaterloo.ca/~mhanis/ece637/lecture7.pdf

There is no significant inductive element in a CMOS inverter, so what is the cause of these peaks while switching?

enter image description here

\$\endgroup\$
3
  • \$\begingroup\$ There is no need for an inductive element. If the rise / fall times of the inverter's input signal are high enough, the Drain-Gate capacitance is sufficient to cause peaks / spikes at the output during the voltage transitions. From my experience, the peaks in this plot are quite small. Use a circuit simulator to simulate an inverter with a square wave input signal. Make the rise/fall times small (a couple of ns) and observe the peaks. Now add a series resistor at the input of the inverter and repeat the simulation. \$\endgroup\$ Nov 10, 2020 at 13:09
  • \$\begingroup\$ @Bimpelrekkie do you mean that the change in Cgd during transitions cause these peaks ? Could you explain what comes in series with what to cause this spike ? \$\endgroup\$
    – spaul
    Nov 10, 2020 at 13:33
  • \$\begingroup\$ do you mean that the change in Cgd during transitions No, you should read more carefully. I talk about signal change. There is a direct path for that signal change: Cgd. It directly couples the input (gate) to output (drain) via Cgd. Simulate an inverter circuit and add a 10 pF capacitor between gate and drain of the MOSFETs. What does the shape of the output voltage look like? \$\endgroup\$ Nov 10, 2020 at 13:43

1 Answer 1

3
\$\begingroup\$

This is an effect caused by the parasitic capacitances of the MOSFET when the input is applied instantaneously. In general, a MOSFET contains five capacitances, namely Cgs, Csb, Cgd, Cdb, and Cgb (as shown in the below figure).

enter image description here

So in the CMOS inverter, we can see the capacitances Cgdp and Cgdn oppose the sudden change in the voltage at the output terminal. So, as Vin increases, the output voltage follows the Vin very little time (as sudden change across the capacitor is opposed) and then falls as expected (due to the NMOS being turned ON). Similarly, while Vin decreases from Vdd, the output voltage falls for a small amount of time and then rises as expected as PMOS turns ON.

enter image description here

Sometimes when the nodes are floating and are not driven to any value, either ground or Vdd, this voltage can jump significantly above Vdd or below ground.

References for figures: The first figure is taken from this link. The second figure is taken from this link. Thanks for the figures to help me convey my answer.

\$\endgroup\$
1
  • \$\begingroup\$ Thanks, @Elliot Alderson for reminding me to cite them. \$\endgroup\$ Jun 9, 2022 at 6:00

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.