I would like to use $random on a single bit input register in Verilog testbench so that it either assumes value 1 or 0 after a delay randomly. How could this be done? The module that I test is an FSM that produces output 1 when the input bits in succession are 1,1 or 0,0

  • \$\begingroup\$ Yeah..I tried initially but were all 0's, now added more of the assignment and got few 1s and 0s as well. Is it possible to specify the number of 1s or 0s we desire? \$\endgroup\$ – yk_learner Nov 12 '20 at 17:49

The distribution of 1s and 0's in each bit for $random is very poor if you just select any specific bit. You will get a better distribution if you use $dist_uniform(seed,0,1). If you want a specific weight of 1's versus 0's, you can do something like

v = $dist_uniform(seed,0,100) < 75; // 3:1 ratio of 1 vs 0.

SystemVerilog gives you much better distributions with $urandom and $urandom_range and has other advantages for random constraints.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.