# Designing lookup table(LUT) for half adder in FPGA

I want to implement half adder using FPGA. For this I need to design CLB, more specifically LUT for half adder. I know LUT gives only one output. But, for half adder we get two output. One for sum and other for carry.

How can I design CLB for half adder?

How can I get two output from LUT? What I am doing wrong?

From study what I understood about FPGA is, This image represent building block of FPGA which is CLB. CLB consists of LUT, D-Flipflop and MUX.

LUT is used to configure any type of logic gates. AND, OR, NOT or any other complex logic gate. By using program we store output of truth table for say AND gate in LUT. And while we give input to FPGA it goes through LUT via address bar and access specific memory address in LUT. And then output of LUT goes through two paths. Here, we need to choose whether we want our output through combinational circuit or sequential circuit. We use MUX for this selecting purpose. 0 for combinational circuit and 1 for sequential circuit.

Am I correct What I understood so far?

When we need to choose sequential circuit and combinational circuit?

• Which FPGA family? Many have special features in their logic block to enable designing adders without a second CLB. But to show you which features, we have to know which FPGA you're targeting. Nov 12, 2020 at 18:19
• You almost never want to directly target FPGA fabric on this scale; you do it sometimes for special functional blocks (memory, IO, DLL, multiplier...), but for basic logic you just write logical (or better yet arithmetic) expressions and lets the tools optimally assign them. In terms of sequential vs combinatorial, you chose what your application needs, but beware that long combinatorial paths between registers will limit achievable clock speeds. Nov 12, 2020 at 18:19
• @ThePhoton FPGA i am using is this: tequipment.net/Digilent/ZedBoard Nov 12, 2020 at 18:39
• Your question is like you want to build an AND gate with transistors in breadboard while you already have dedicated chips for that. Why you wanna even do it when the while point of designing in FPGA is TO MAKE USE OF CLBs WHICH ARE ALREADY THERE IN FPGA. Nov 13, 2020 at 3:41

As mentioned by Chris in comments, rather than try to manage all this complexity yourself, with modern synthesis tools (i.e. tools developed in the last 20 years), you'll usually achieve better results by just writing assign X = A + B; in your Verilog than by trying to configure the CLB yourself.