I want to implement half adder using FPGA. For this I need to design CLB, more specifically LUT for half adder. I know LUT gives only one output. But, for half adder we get two output. One for sum and other for carry.
How can I design CLB for half adder?
How can I get two output from LUT? What I am doing wrong?
From study what I understood about FPGA is, This image represent building block of FPGA which is CLB. CLB consists of LUT, D-Flipflop and MUX.
LUT is used to configure any type of logic gates. AND, OR, NOT or any other complex logic gate. By using program we store output of truth table for say AND gate in LUT. And while we give input to FPGA it goes through LUT via address bar and access specific memory address in LUT. And then output of LUT goes through two paths. Here, we need to choose whether we want our output through combinational circuit or sequential circuit. We use MUX for this selecting purpose. 0 for combinational circuit and 1 for sequential circuit.
Am I correct What I understood so far?
When we need to choose sequential circuit and combinational circuit?