# LTspice: behavioral modelling elements for propagation delay

I'm trying to create a subcircuit in SPICE (currently using LTspice but want a pretty agnostic model) for an AND gate that delays an input by some amount TPD.

I'm currently just inputting 2 offest clock signals to the following subcircuit:

.SUBCKT AND_GATE_TEST A B OUT VCC VEE
XOUTLOGIC A B OUT_LOGIC VCC VEE LOGIC_FUNCTION
XOUTPD OUT_LOGIC OUT VCC VEE PD_FUNCTION
.ENDS

************************************************************

.SUBCKT LOGIC_FUNCTION  A B OUT VCC VEE

GAND VEE N1 VALUE = {V(A,VEE)*V(B,VEE)}
RN1 N1 VEE 1
EOUT1 OUT VEE N1 VEE 1

.ENDS

************************************************************

.SUBCKT PD_FUNCTION IN OUT VCC VEE

GDEL VEE N1 VALUE = {V(IN,VEE)}
RN1 N1 VEE 1
EDEL = OUT VEE DELAY N1 VEE TD=10ns

.ENDS


The first logic function works fine and outputs the expected AND logic given the inputs A and B but I get tripped up with the propagation delay function.

The error that LTspice outputs says Missing gain value but no matter how I use the E element (or any behavioral elements for that matter) as a delay function I can't get it to work properly.

I think I'm missing something fundamental on the syntax of the behavioral elements

Any help on how to best approach this would be greatly appreciated.

What you have there is not exactly an AND, because if the inputs don't have logical levels of [0:1], you're in trouble. And that syntax is not SPICE friendly, so it must be some proprietary way of defining a delay.

For an agnostic model you could use a behavioural source and a transmission line with:

B1 0 1 I = V(a) & V(b)
T1 1 0 out 0 Td={td} Z0=1
R1 out 0 1


where I used & for the logical AND. IIRC, ngspice uses &&, others may have their notations, as well, but the behavioural source shoud be SPICE compatible. If not, at the expense of manually setting the output levels, you could use:

I = Vlow + (Vhigh - Vlow) * ( ( u(V(a) - (Vhigh + Vlow) / 2) ) * (u(v(b) - (Vhigh + Vlow) / 2 ) ) )


I think u() is SPICE compatible. I've also avoided the use of the builtin delay() (or absdelay()) because 1) it might be particular to LTspice (or only a few), and 2) the tline is SPICE compatible (and better behaved for fixed delays). The output resistance can be changed to have other values, in which case the expression in the current source would have to be changed to (<expression>)/R and the transmission line's impedance to Z0={R}.

Otherwise, if you can tolerate an LTspice-only solution, I would highly recommend the builtin A-device [Digital]/and with td={td} (you may also want to use tau and tripdt, or vhigh, vlow, etc, see more in the help).

• Thanks for your help. I didn't realise it could be so easy using a transmission line. I was basing my code off of a Texas Instruments simulation file. Their logic function was the same as mine but I believe they then go an normalise it afterwards to output the correct voltage level. Nov 17, 2020 at 3:08
• I'm a little confused about the reason we need R1 across the output and the role the characteristic impedance plays on the output? When simulating this model I get the exact transient response as the data sheet I am basing this off but don't understand why. I assumed that an 'ideal' transmission line would only delay the output by some time Td, and not have any transient response. I guess that Z0 is comprised of some RCL equivalent which results in a transient across the output? Nov 19, 2020 at 2:04
• @iagreewithjosh Z0 is the characteristic impedance with wich the transmission line must be terminated in order to avoid reflections. Unless you want those reflections (for your case you don't) you have to match the terminating resistance with Z0 (the gain will be half). Normally, you would need another matched resistance at the other end, but I am relying on this being a current source, which will see the output resistance as the load, through the tline. Nov 19, 2020 at 10:20
• I see, that makes sense. So if I put in another resistor before the transmission line and change the source to a voltage source, I can model the nominal input and output resistances of the gate (say 50 ohms)? As long as the characteristic impedance is also set to 50 to avoid reflections? Another quick question, it seems that Spice uses 0.5 V as the threshold for the logic expression. Is there a simple way to change this to some other value? Or will the logic expression have to be rewritten to something along the lines of the equation in your original answer to achieve this? Nov 23, 2020 at 1:23
• @iagreewithjosh Since this is SPICE, no smoke will come out, so whether it's a V or I source, you don't have to add an input (matching) resistance; the output is what matters. For V source, no change is needed, but for I source, if Ro=50, then you need to modify the expression to be <expression>/50. The threshold defaults to (vhigh+vlow)/2, but that can be changed. How, it depends on the implementation. In LTspice, for A devices, it's as simple as ref=<...>, or vt=<...> for Schmitt gates. In my example I assume it's half, but you can change that to be -1 kV, if you really wish. Nov 23, 2020 at 10:37