I used to work with Lattice FPGA (Lattice ECP3) and I used to have this primitive: IDDRX2D1
enter image description here

the block internal circuit: enter image description here

I can't find an equivalent for this kind of input DDR in Xilinx Series 7 libraries,
the closest thing I found is this: enter image description here
which is similar except that it's not 2x gearing, I need 4 outputs like the primitive from Lattice. Any ideas if such a thing exists in Xilinx primitives?

  • \$\begingroup\$ Isn't this a question for the Xilinx support forums instead of here? \$\endgroup\$
    – TonyM
    Nov 16, 2020 at 15:56
  • 1
    \$\begingroup\$ May be ISERDES ? \$\endgroup\$
    – maximus
    Nov 16, 2020 at 17:38

1 Answer 1


ISERDES is what you are looking for. 7-series libraries guide will give information about the instantiation of the ISERDES. But UG471 - 7 Series FPGAs SelectIO Resources User Guide will give more information on ISERDES. (You might find some other interesting components).

enter image description here


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