I used to work with Lattice FPGA (Lattice ECP3) and I used to have this primitive: IDDRX2D1
I can't find an equivalent for this kind of input DDR in Xilinx Series 7 libraries,
the closest thing I found is this:
which is similar except that it's not 2x gearing, I need 4 outputs like the primitive from Lattice. Any ideas if such a thing exists in Xilinx primitives?