# Why would the intersection of logic 1 and logic 0 results in logic 0?

Below is an illustration on how coincident decoding works in which the total number of gates used in the decoder can be reduced by employing two decoders in a two‐dimensional selection scheme:

If x-output 12 and y-output 20 is both logic one, then the intersection(colored orange) will be logic 1 right? But what about the others? For example, if x-output 0 and y-output 20 is logic 0 and 1 respectively, how will the interestion(colored green) will remain disabled(logic 0) and the orange colored intersection to be the only one active(logic 1)?

Why would the intersection of logic 1 and logic 0 results in logic 0?

I thought that the intersection would mean the logic 1 being shorted to logic 0 that's why the result will be grounded(logic 0),but I doubt this since this would mean that every disabled intersections of the RAM block will be shorted and that sounds bad to me....

The diagram show is a high-level view of the decoding structure, it's not representative of the actual circuit.

The intersection points where it shows a dot are not intended to show that the two signals are physically shorted together (like you would find in an electrical schematic), but rather the dot represents a memory cell - in this diagram a dot seems to show a disabled cell, and a non-dot shows the enabled cell.

In a physical circuit you would have some access logic such as pass transistors on a grid of bit lines. The row decoder would enable the pass transistors for each cell on that row which enable that row to drive each of the column signals. Then the column decoder then routes the signal to/from just one of the column lines, thereby selecting just one active cell.

Why would the intersection of logic 1 and logic 0 results in logic 0?

It doesn't have to. The logic result of two inputs depends on the type of logic function used. If the two inputs (x and y) go into an AND gate, then for three input conditions the output is a 0, and only for the (1,1) input the output is a 1. In a selection matrix such as your, this is the usual method.

As an example of some other function, if you have a NAND gate at each intersection, then the output is high for either (0,1) or (1,0), and is low only when the inputs are (1,1).

Augustas Demorgan, back in 1840, proposed philosophies suited to your question.

Why think this way? It underpins mathematical deduction.

• While you're right, I don't think it's necessary nor is it helpful to dive into the mathematical background of discrete structures to answer this question. Nov 17 '20 at 19:23