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I'm working through Joseph Cavanagh's Digital Design and Verilog HDL Fundamentals. In chapter 3, he discusses using (+) and (-) in front of bits to indicate active high and active low signals, i.e.

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I understand the concept of active low, where a logical 0 is a TRUE. And I think I understand what he's saying for figure (a), the equation is -z1 = (x1x2), and for (b), in order to get -z1, the active low signal, the equation is (x1x2'). What I want to make sure I understand are the semantics, for lack of a better term, of figure (b). x1 is active high, x2, because of the (-) is active low, so in order to drive z1 low (i.e., -z1), x2 has to be negated so that -x2 becomes x2 (i.e, x2').

I was interpreting figure (b) as NAND(1, 0) = z1, and what we want is NAND(1, 0') = -z1, but the discussion of active high and active low was confusing me. I think what I would like is confirmation my interpretation of figures (a) and (b) are correct. Or that I am over analysing this.

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    \$\begingroup\$ So far as I know, this notation (\$-x_1\$ to indicate logical negation of \$x_1\$) is not common outside of that particular book. So you'll have to look to that book to find out the details of how it is interpreted. \$\endgroup\$
    – The Photon
    Nov 18 '20 at 2:11
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    \$\begingroup\$ IMHO you've overanalyzing, and the book author did moreso. The behavior of gates is what it is, reflecting actual levels. "Active High" vs "Active Low" relates to how meaning is assigned to those levels, eg which one enables the cookie dispenser. But it does not change how they are treated in the sense of combinatorial logic. \$\endgroup\$ Nov 18 '20 at 2:11
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For figure (a):

           -z1 = x1 & x2
            z1 = (x1 & x2)' (NAND operation)

For figure (b):

          -z1 = x1 & x2' 
        => z1 = (x1 & x2')' (Taking complement on both sides)
        

Here & stands for the and operation.

so in order to drive z1 low (i.e., -z1), x2 has to be negated

It is not correct to say an input is negated, instead, we say a LOW on x2 and a HIGH on x1, produces a LOW on z1.

So z1 = x1 NAND x2' in the case of figure (b).

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