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I'm designing a BON testing fixture for a complex board (multiple processors, fpga, memory, etc).

One of the items to test is an external ethernet connection (1Gb). In the current design, the ethernet PHY is internal to the processors SOC. This board is connected to an I/O board that houses the RJ45 connector and magnetics. The two boards are connected via a FFC cable.

We were thinking about exposing the ethernet signals on pads so we can access and test with BON, but we are concerned with piping high speed signals through a nail and wires to the testing board...

Any advice?

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    \$\begingroup\$ 10/100 or GbE?? \$\endgroup\$
    – user16324
    Commented Nov 18, 2020 at 20:29
  • \$\begingroup\$ we are using 100Gb \$\endgroup\$ Commented Nov 19, 2020 at 0:07
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    \$\begingroup\$ Most 100Gb media seems to be fiber-optic... you're using Twinaxial or copper-backplane? \$\endgroup\$
    – rdtsc
    Commented Nov 19, 2020 at 13:06
  • \$\begingroup\$ Sorry, I misspoke, it's 1Gb... \$\endgroup\$ Commented Nov 19, 2020 at 18:16

2 Answers 2

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It's worth remembering that ethernet is designed with a fair bit of margin for poor wiring. You can actually get away with a fair bit of divergence from recommended wiring practices over short distances. Think about the discontinuities that ethernet signals encounter as they pass through lowest-bidder wiring infrastructure. With some care, you can create a bed of nails test setup that is probably less problematic in terms of wiring geometry (and hence signal integrity) than the average office wiring job.

I've not done this for gigabit, but I have test fixtures that use pogo pins for 100Mb ethernet, and they've given me no trouble at all. Just keep the rest of your wiring and board routing neat and to spec (proper impedances, length matching, etc -- and remember that lengths should be matched across the total length between the two phys!), and keep the contacts for each of the ethernet pairs together and preferably somewhat separated from the other pairs. Plus, test points are basically free, so you can throw them onto the PCB, and if they work, great, if not, you haven't lost much.

Another thing to consider, do you actually need to run the interface at gigabit speeds when it's in the test fixture? Obviously you do if the point is to test the netif hardware, or you need the speed to move a lot of data or whatever, but if you can get away with 100Mb you only need half the contacts and the wiring will be even more forgiving.

(Just be aware that you can't always connect two gigabit terminals with only four wires and get a link. This is because link negotiation happens on the two primary pairs, so two gigabit phys will still agree to link at gigabit, but then will fail to establish that link because of the two missing pairs. Some terminals will fall back to 100Mb if the gigabit link fails but not all, and those that do may take a while -- I've seen it take ~10 seconds to get a link up in that scenario. If you can configure one end of the link to not advertise gigabit capability that will avoid the issue.)

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What are you trying to test? Usually bed of nails tests at the PCB level are intended to catch manufacturing defects. They are not intended for validating layout and signal integrity. Likewise, the IC should be already known good and tested. So all you have to do in your test is verify that you don't have opens or shorts on the Ethernet lines. Is it possible to do something simple like drive the Ethernet lines as IO's and loop them back in the test fixture so that you can test for opens and shorts and stuck high and stuck low? No need to exercise the lines as Ethernet signals.

If the IC won't allow you to drive the ethernet pads as IO's, then my idea might not work.

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