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I was writing Verilog code for an ALU from the nand2tetris course
This code compiled without any errors in ModelSim but when I try to start simulation it throws an error Error loading design Instantiation of 'addtwobit' failed. The design unit was not found.
P.S- Kindly ignore the use of many always blocks.

module alu(x,y,zx,zy,nx,ny,f,no,op);

    input[1:0]x,y;
    input zx,nx,zy,ny,f,no;
    reg [1:0]zxx,zyy,nxx,nyy,fo;
   wire [1:0] zxxn,zyyn,anf,adf;
    wire zxx1,zxx2,zyy1,zyy4,fo1,fo2,co;
    output reg [1:0] op;
    
    always @(*)
    begin
    case(zx)
    1'b0:zxx=x;
    1'b1:zxx=0;
    endcase
    
    case(zy)
    1'b0:zyy=y;
    1'b1:zyy=0;
    endcase

    end
    
    not n1 (zxx1,zxx[0]);
    not n2 (zxx2,zxx[1]);
    assign zxxn={zxx2,zxx1};
    
    not n3 (zyy3,zyy[0]);
    not n4 (zyy4,zyy[1]);
    assign zyyn={zyy4,zyy3};
    
    always @(*)
    begin 
    case(nx)
    1'b0:nxx=zxx;
    1'b1:nxx=zxxn;
    endcase
     case(ny)
     1'b0:nyy=zyy;
     1'b1:nyy=zyyn;
     endcase
     end
     
     and a1(anf1,nxx[0],nyy[0]);
     and a2(anf2,nxx[1],nyy[1]);
     assign anf={anf2,anf1};
    
    
    addtwobit(nxx,nyy,adf,co);
    
    always @(*)
    begin 
    case(f)
    1'b0:fo=anf;
    1'b1:fo=adf;
    endcase
     end
      not n5 (fo1,fo[0]);
    not n6 (fo2,fo[1]);
    assign fno={fo2,fo1};
     
    
    always@(*)
    begin 
    case(no)
    1'b0:op=fo;
    1'b1:op=fno;
    endcase
    end
    
    task addtwobit;
    input reg [1:0]nxx,nyy;
    output reg [1:0]adf;
    output reg co;
    begin
    //xor x1(adf[0],nxx[0],nyy[0]);
    //xor x2(adf[1],nxx[1],nyy[1]);
    
    //and a1(coo[0],nxx[0],nyy[0]);
    //and a2(coo[1],nxx[1],nyy[1]);
    //or o1(cof,coo[1],coo[0]);

    //adf={adf[1],adf[0]};
    adf={nxx[1]^nyy[1],nxx[0]^nyy[0]};
    co=(nxx[0]&nyy[0])|(nxx[1]&nyy[1]);
    end
    endtask
module alu_dut2;
reg [1:0]a,b;
reg zx,zy,nx,ny,f,no;
wire [1:0]op;
alu alutb(.b(y),.zx(zx),.a(x),.zy(zy),.nx(nx),.ny(ny),.f(f),.no(no),.op(op));
initial 
begin 
$monitor($time,"a=%d , b=%d zx=%d , zy=%d , nx=%d , ny=%d , f=%d , no=%d , out=%d",a,b,zx,zy,nx,ny,f,no,out );
#5 a=3;b=2;zx=0;nx=0;zy=1;ny=1;f=0;no=1;
#5 a=3;b=2;zx=0;nx=0;zy=0;ny=0;f=1;no=0;
#5 a=3;b=2;zx=0;nx=0;zy=0;ny=1;f=1;no=1;
#5 a=3;b=2;zx=0;nx=0;zy=0;ny=0;f=0;no=0;
#5 $finish;
end 
endmodule
    
endmodule
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  • 1
    \$\begingroup\$ please format your code with proper indentation levels \$\endgroup\$ – jsotola Nov 19 '20 at 21:16
  • 1
    \$\begingroup\$ How about a minimum example that shows your problem, please? And welcome to the site. \$\endgroup\$ – Brian Carlton Nov 19 '20 at 23:44

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