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When you get into the single digit pF capacitors, the capacitance approaches what could be achieved with only a trace (which wouldn't be changeable, but I don't care about that).
Quick calculations tell me that a 5mil trace a 0.6" long would give me about a pF for a clock signal. (or you could do just a pad)
Have you ever seen this done or tried this on FR4?
Yes, people (including myself) do sometimes use PWB traces to create capacitance or resistance. Often the high tolerances create enough problems that its not worth the space/cost saved by not using a discrete component.
The particular capacitor you propose would likely have over 50% tolerance.
A better geometry would be something a 50 mil x 50 mil square. The copper feature tolerance would have much less of an impact and so the tolerance would likely be much closer to 20% in that case (rather than 50%). Additionally a square would have much lower inductance.
There are PCB materials specifically sold for the purpose of creating "embedded capacitance" or "embedded resistance".
Embedded capacitance material typically has a higher dielectric constant than regular FR4, so you get more capacitance per square inch. One typical application is to put the embedded capacitance material between the power and ground planes, so that the plane capacitance increases. This can reduce the plane impedance enough that you can just put decoupling capacitors regionally rather than next to every IC. This can potentially save a lot of capacitors.
Actually it is routinely being done, but only if no such component is available or they are not practical. The design and characterization requires time, which could be saved, or reduced if an off-the-shelf component would have been used. SMD capacitors with values smaller than 1pF are available.
You can always create a small capacitance value with series connection of multiple capacitors if the series resistance and inductance does not matter. That could be also a way to go.
In RF design, matching networks are used to avoid reflections and get out the maximum power from a given device. The simplest case, where I've used a trace capacitance was when I needed to match a bondwire chip connection to a transmission line of the PCB.
In a PCB --- or in any lithographic process --- the trace width is not well controlled. The thinner the copper and the higher the resolution of the technology is, the better. The substrate thickness is fairly well controlled, especially in substrates intended for RF applications. I have no information about FR4, but you can ask such data from your manufacturer. Therefore I would use the capacitance between metal layers, rather than the capacitance between traces of the same metal layer. Especially if you have a ground plate there, its easy to do. If the capacitance value is critical you might run some EM simulation, or parasitic extraction tool, but if you have no licence for such tools, a test PCB run and measurement might do the trick. Since the trace width inaccuracy will alter the plate area of your capacitor a circular cap would fit the best.
