Will multiple SPI slaves lower data transmission?

I'm working on a project that requires rather high data transmission to a larger number of SPI slaves.

Will connecting multiple SPI slaves to the same master lower the througput alot? The master wont be able to communicate with all SPI slaves at the same time, so I'm guessing there will be a drop. But how do you determine the drop?

Thanks

Edit: Each slave has a data bit rate up to 8 Mbps. I need 12 slaves connected and have 6 masters matching this.. However, I was thinking of reservering a number of master's for later addition of slaves, should it be needed, and thereby having 3 slaves per master. I understand the point, that each master can only communicate with one slave at a time, meaning that they will share the throughput. This was the reason for my initial question.

• By estimating how much you need to talk to each device in some unit of time, with the given SPI bus speed. Nov 20, 2020 at 12:18
• You should be more explicit. "large number", "high transmission rate", etc... don't mean much. Is your "large number" 10 devices? In that case, it's probably insignificant. 1000? In that case, it certainly won't work at all, whatever speed you plan to use, for other reasons. What is exactly the speed you want to reach? How will the bus be wired? What is its length? Datasheet of the master? Datasheet of the slaves?
– dim
Nov 20, 2020 at 12:21
• This is much too vague a question to get any kind of reliable answer and there's no 'single rule' on 'a lot'. Please edit your question and put a specific instance in, with the two sets of SPI characteristics you're considering between. Nov 20, 2020 at 12:24
• Maximum payload is shared by the number of slaves. Nov 20, 2020 at 12:27

Since SPI is a bus, the bus is shared between all connected components. With a single bus, the communication at any time is limited to a single pair of SPI master and slave. It's not possible to communicate with two slaves concurrently.

A single bus will have a lower transmission rate compared to two or more SPI buses working concurrently.

However, if you your code does not take advantage of concurrency (i.e. is not neither using DMA transfers nor multiple tasks in an RTOS), it will only communicate on a single SPI bus at at any time. In that case, the data rate of a single bus is the same as multiple buses.

In short:

• If your code can take advantage of concurrency, multiple SPI buses offer higher data bandwidth.
• If your code does not take advantage of concurrency, multiple SPI buses offer no advantage.

Also check if the SPI bandwidth is really a limiting factor. If not, there is nothing to be gained with complex code and multiple SPI buses.

• Great answer, this is exactly what I was wondering. The master has a quadcore cpu, so concurrency should definately be possible. Data rate of each is up to 8 Mbps, so I think its important there is a master to each slave. Nov 20, 2020 at 13:41

Let's analyze the worst case - all slaves require communication 100% of the time. Obviously, the worst case rate would drop to 1/# of slaves. If the duty cycle is less than 100% than the worst case rate would not be as bad.