I have an inquiry and searching on Google didn't help. If I have a voltage regulator, with active low shutdown pin, and the output of the voltage regulator powers an FPGA/ASIC/CPLD, how can I implement a "hand-off" circuit paired with this voltage regulator such that the FPGA turns on when the voltage regulator is initially powered on, but the FPGA can turn itself off by driving the shutdown pin low, and keep this voltage regulator off? By the way on this voltage regulator, the active low shutdown pin, when either tri-stated or driven high both keep it enabled. So it MUST receive a logic low.
If my specific question doesn't make since, I'll ask a more general question: How can an FPGA power itself off with a shutdown signal to the circuit which powers it?
Thanks in advance!