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I have an inquiry and searching on Google didn't help. If I have a voltage regulator, with active low shutdown pin, and the output of the voltage regulator powers an FPGA/ASIC/CPLD, how can I implement a "hand-off" circuit paired with this voltage regulator such that the FPGA turns on when the voltage regulator is initially powered on, but the FPGA can turn itself off by driving the shutdown pin low, and keep this voltage regulator off? By the way on this voltage regulator, the active low shutdown pin, when either tri-stated or driven high both keep it enabled. So it MUST receive a logic low.

If my specific question doesn't make since, I'll ask a more general question: How can an FPGA power itself off with a shutdown signal to the circuit which powers it?

Thanks in advance!

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  • \$\begingroup\$ This would rarely be done; but if you want to, consider a clamped series capacitor to the input and then a sustainer output from the logic device. Common with an MCU; with an FPGA you have the additional headache of needing to get started up and operation quickly, eg, you probably need a way to "wedge" it when developing and configuring the FPGA rather than having it quickly read a config ROM. \$\endgroup\$ – Chris Stratton Nov 20 '20 at 21:00
  • \$\begingroup\$ One approach is to keep some state outside the FPGA. Perhaps in a 74HC74 flip flop which remains ON even when the FPGA is OFF, to drive the shutdown signal. \$\endgroup\$ – user_1818839 Nov 20 '20 at 21:04
  • \$\begingroup\$ That's what power controllers are for. I certainly wouldn't make product recommendations, because that's against the rules. Coincidentally, I've seen this part in a few of my circuits: LTC2955. I'm sure that there are others... \$\endgroup\$ – Chris Knudsen Nov 20 '20 at 21:57
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This might work – see circuit below.

On power up, both sides of C jump to the rail (VP) and the regulator turns on.

C starts charging through R and at some point the shutdown voltage (dotted line in the expertly drawn Fig. 1 below) will be reached and the regulator will turn off.

To prevent that, we need to make the RC time constant large enough that the FPGA has time to get configured (on the order of 100mS if booting directly from Flash), and that the output pin is initially configured to drive its ouput pin high immediately.

Fig. 2 shows the FPGA configuration happening at t1 and driving the output pin high. Of course, the FPGA output voltage minus the D1 diode drop must be higher than the shutdown voltage for this to work.

When the FPGA decides to power itself down (at t2) it drops the output low and the shutdown pin voltage decays to zero, shutting down the regulator.

The diode D1 is there to protect the FPGA, only really necessary if VP is a higher voltage than the FPGA pin can tolerate.

The diode D2 is there to quickly discharge C when power is truly turned off, so that circuit works if power turned back on quickly.

enter image description here

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