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I'm learning the DDR4 technology and I don't understand how the DIMM/component can change its CL automatically.

FPGAs/ASICs can basically choose the frequency to apply to the DIMM/component.

  • Why do we stick with the standard's ones? (2400/2666/2933/3200)

DIMM/component can be downgraded to use a lower frequency. Let's say even though the DIMM supports 3200, it still can run at 2666. Nevertheless, in the datasheet, lots of timings and especially the CAS latency/CL change with the frequency (or MT/s).

  • Why? How does the DDR4 module knows which CL to apply?

For the Xilinx's ddr4 controller, we need to provide lots of timings, why does it need these? How does a motherboard know about all these timings for all the specific DIMM modules?

(tCKE,tFAW,tMRD,tRAS,tRCD,tREFI,tRFC,tRP,tRRD_S,tRRD_L,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,cas latency,cas write latency)

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The memory controller configures the chip by telling it at startup which CL value is to be used before using it.

It just takes certain amount of time for the data to be ready after sending the read command. Thus different bus speeds need different CL values, to make sure that enough time has passed before data is sent on the bus. So by lowering the clock speed, at some point the CL can also be lowered.

The clock speeds are multiples of 33.33 MHz, a lot of the timing is based on some base clock value that can be multiplied to get higher frequencies. Note that 33.33 MHz is not some mysterious magic value, but one third of 100 MHz, and many motherboards use a 25 MHz crystal clock oscillator to get multiples of 100 MHz to begin with.

A DIMM module is a bit special, as it contains a separate memory chip that contains information about the module timing, and this memory chip can be read by the motherboard to know which speeds and timings are supported by the module, and then configure the clock and memory controller accordingly.

So if you are connecting a DRAM chip directly to an FPGA, there is no way for it to auto-detect the timing, and you must tell the memory controller all the parameters that are relevant for using the memory, including the clock speed and CL timings, and tons of more timings so that the memory chip is used properly within its specifications.

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  • \$\begingroup\$ Thanks! Is the chip the EEPROM accessible via I2C? The xilinx MIG controller doesn't use the I2C, that's why it needs all the values upfront. Understood! \$\endgroup\$
    – None
    Commented Nov 21, 2020 at 1:11
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    \$\begingroup\$ Indeed, there is typically a 24xx type of I2C chip on DIMM modules. \$\endgroup\$
    – Justme
    Commented Nov 21, 2020 at 1:13
  • \$\begingroup\$ Understood, regarding the CL, in a datasheet, it's frequent to see 2 different CL for the same frequency. (eg CL=22 or 21 for 2933MT/s) Which one is the right one? CL isn't configurable, it's a property of the DRAM then I don't understand that. Also, I believe the PCB trace length has an impact on that timing too.. \$\endgroup\$
    – None
    Commented Nov 21, 2020 at 1:15
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    \$\begingroup\$ If both are supported at the speed you use, both are right ones and you need to choose. In my answer, the first thing I said that CL is configurable, and the memory chip must be told which CL to use. It might support a single value or a range of values for a given clock rate. I am not sure how PCB trace length (i.e. time of flight) would affect CL. \$\endgroup\$
    – Justme
    Commented Nov 21, 2020 at 9:58
  • \$\begingroup\$ Understood, it isn't magic and needs to be programmed. Now it makes sense. Thanks! \$\endgroup\$
    – None
    Commented Nov 21, 2020 at 10:16

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