I'm learning the DDR4 technology and I don't understand how the DIMM/component can change its CL automatically.
FPGAs/ASICs can basically choose the frequency to apply to the DIMM/component.
- Why do we stick with the standard's ones? (2400/2666/2933/3200)
DIMM/component can be downgraded to use a lower frequency. Let's say even though the DIMM supports 3200, it still can run at 2666. Nevertheless, in the datasheet, lots of timings and especially the CAS latency/CL change with the frequency (or MT/s).
- Why? How does the DDR4 module knows which CL to apply?
For the Xilinx's ddr4 controller, we need to provide lots of timings, why does it need these? How does a motherboard know about all these timings for all the specific DIMM modules?
(tCKE,tFAW,tMRD,tRAS,tRCD,tREFI,tRFC,tRP,tRRD_S,tRRD_L,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,cas latency,cas write latency)