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I'm aware that terms like "5 nm", "7 nm" for the latest technology nodes no longer refer to any linear dimension of the transistors, although I have seen some interpretations in terms of pitch. My understanding is that the names are arbitrary and just following what the naming convention used to be when they really did correspond to the gate lengths. As far as I can tell, a new process is defined according to milestones in achievable transistor density.

For these 5 nm, 7 nm, etc. processes, what is the actual shortest allowable channel length? Though new transistors look very different from the CMOS devices from 30 years ago my understanding is that there is still a definable channel length if not a clear gate length equivalent (e.g. for FinFETs).

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