I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of.
Figure 2.7 shows a DRAM chip at a very high level. The DRAM cells are organized in rows and columns. They could all be aligned in one row but then the DRAM chip would need a huge demultiplexer. With the array approach the design can get by with one demultiplexer and one multiplexer of half the size.
I can understand that there are a lot of reasons for a memory array to be laid out as a square. But why would you need a huge demultiplexer if all the memory cells were aligned in a single row? First of all, if they were aligned on a single row then wouldn't the CAS multiplexer be huge instead? If there's only one row to select then you wouldn't need a demultiplexer to select the correct row. If I trusted myself on this then I would just think that they mistyped and meant to write They could all be aligned in one column.
And secondly, why does the combined size of the demultiplexer and multiplexer become smaller with the array based structure instead of just having a single row? Or am I misunderstanding the snippet somehow? Is one demux with 15 address lines together with one mux with 15 address lines smaller than one demux/mux with 30 address lines?
I do know about multiplexing address lines so that you can use the same set of address lines for both row and column selection. But because the paper mentions this feature a few paragraphs after the displayed quote, I'm assuming that it's not meant to be taken into account yet. If it's relevant.
Apologies if my use of different terminology is incorrect. My only experience with this topic is through this paper and what I've researched online to try and understand it. Especially the title, I couldn't think of a better one.