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I'm reading the chapter about DRAM access (2.1.3) of the paper "What Every Programmer Should Know About Memory - Ulrich Drepper" and there's a certain snippet that I just can't make sense of.

Figure 2.7 shows a DRAM chip at a very high level. The DRAM cells are organized in rows and columns. They could all be aligned in one row but then the DRAM chip would need a huge demultiplexer. With the array approach the design can get by with one demultiplexer and one multiplexer of half the size.

Figure 2.7

I can understand that there are a lot of reasons for a memory array to be laid out as a square. But why would you need a huge demultiplexer if all the memory cells were aligned in a single row? First of all, if they were aligned on a single row then wouldn't the CAS multiplexer be huge instead? If there's only one row to select then you wouldn't need a demultiplexer to select the correct row. If I trusted myself on this then I would just think that they mistyped and meant to write They could all be aligned in one column.

And secondly, why does the combined size of the demultiplexer and multiplexer become smaller with the array based structure instead of just having a single row? Or am I misunderstanding the snippet somehow? Is one demux with 15 address lines together with one mux with 15 address lines smaller than one demux/mux with 30 address lines?

I do know about multiplexing address lines so that you can use the same set of address lines for both row and column selection. But because the paper mentions this feature a few paragraphs after the displayed quote, I'm assuming that it's not meant to be taken into account yet. If it's relevant.

Apologies if my use of different terminology is incorrect. My only experience with this topic is through this paper and what I've researched online to try and understand it. Especially the title, I couldn't think of a better one.

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    \$\begingroup\$ The explanation is garbage. The size of the MUX and demux is NOT half the size! It's log2 * sqrt(N) the size which is ONLY half the size for the special case of N=16, sqrt(N) = 4 and log2(4) = 2. Redraw with 1 million cells : you now need mux/demux of 10 bits (1024 in/outputs) each ... MUCH smaller than a single 20-bit demux with a million inputs! \$\endgroup\$
    – user16324
    Nov 21, 2020 at 14:00
  • \$\begingroup\$ @BrianDrummond What is N supposed to be in this formula? Could you run through the example of a million cells that you presented to me so I can confirm whether I'm understanding correctly or not? \$\endgroup\$ Nov 21, 2020 at 22:04
  • \$\begingroup\$ Number of storage cells : 16 in your illustration which is too small to show any advantage in the square matrix. Example : 1 million cells : square needs mux/demux of 10 bits (1024 in/outputs) each ... MUCH smaller than a line with a single 20-bit demux with a million inputs \$\endgroup\$
    – user16324
    Nov 22, 2020 at 0:07
  • \$\begingroup\$ @BrianDrummond So if the size is calculated with the formula log2(sqrt(N)) where N is the number of inputs or outputs. For a square layout with a million cells there is one mux and one demux, each have 1024 in/outputs. log2(sqrt(1024)) = 5, since there is one mux and one demux the size is 5+5=10. For a line with 1024*1024 (a million) inputs the size would be log2(sqrt(1024*1024)) = 10. Isn't the size the same for both square and line layouts? \$\endgroup\$ Nov 22, 2020 at 13:34
  • \$\begingroup\$ No. The size of a demux is controlled by its number of outputs. A demux with a million outputs has size of order 1 million. The size of two [demuxes!muxes] each with 1023 [outputs!inputs] is of order 1024. * 2 (not 1024^2). Much smaller. \$\endgroup\$
    – user16324
    Nov 22, 2020 at 13:42

2 Answers 2

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Mostly collated from comments.

The explanation is garbage. The size of the MUX and demux in the square array is NOT half the size! It's log2 * sqrt(N) the size, versus the size of the linear storage array (vector) which is log2(N).

This is ONLY half the size for the special case of N=16, sqrt(N) = 4 and log2(4) = 2, versus a 16 element linear array whose decoder size = log2(16) = 4.

Redraw with 1 million cells! you now need mux/demux of 10 bits (1024 in/outputs) each ... MUCH smaller than a single 20-bit demux with a million inputs!

The crucial point (which gets lost in the linked explanation thanks to its unfortunate choice of 16 elements) is that two structures of size O(1024) are much smaller than a single structure of size O(1 million), which would be required to access 1 million elements in a single vector. This structure would be at least as large as the memory array itself!

Incidentally Elliot's point that the capacitances also increase (reducing speed) as the structure size increases is also true; that is definitely a design consideration but not the only (and probably not the main) one.

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I think the real reason that memory arrays tend to be square is because of the \$RC\$ time constant of the wordline and the bitlines. Both the resistance and the capacitance of a long thin wire are proportional to its length, so the \$RC\$ time constant is proportional to the length squared. To minimize the sum of the \$RC\$ time constants of the wordline and the bitline, a square array is used.

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