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I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense until one of my classmates told me he could implement an AND gate with four transistors, much like a NAND gate but with some symmetry. I implement his idea using Logisim (see the image below, the left one is a NAND gate, and the right one is a four-transistor AND gate I think of), and it seems the circuit I conceive works. So could anyone explain to me why an AND gate needs six transistors?

four-transistor NAND gate and four-transistor AND gate

Thanks in advance!

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    \$\begingroup\$ Simulators don't put up much of a fight. See whether your classmate's circuit can drive a 1k Ohm load, or a 100 Ohm load. Can it drive an LED by pulling the cathode low? If you could make an AND gate just as good as a NAND gate with 4 transistors you can probably collect a noble prize for your trouble. \$\endgroup\$ – mkeith Nov 22 '20 at 9:11
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    \$\begingroup\$ Logisim is for simulating digital logic circuits only. Simulations of transistors would be inaccurate in Logisim. \$\endgroup\$ – Shashank V M Nov 22 '20 at 11:21
  • \$\begingroup\$ To add to confusion, there are (used to be? ) alternative logic setups. These would typically use fewer transistors. Examples include diode-transistor and resistor-transistor (both have articles on wikipedia). \$\endgroup\$ – ghellquist Nov 23 '20 at 6:43
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    \$\begingroup\$ I would suggest trying with real transistors :) You can get an "and" gate without any transistors, but what do you get on output? Just because it works with a LED or in a (digital logic!) simulator doesn't mean it will actually work in a real circuit, in particular, when you start chaining gates together. Playing around with a solderless breadboard is very illuminating - in particular, I've learned early on to use a couple more transistors than strictly necessary, especially when trying to keep the power drain down :) \$\endgroup\$ – Luaan Nov 23 '20 at 14:15
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    \$\begingroup\$ There's a difference between designing an ad-hoc logic circuit that stands alone by itself, and building a gate that belongs to a specific, systematic logic family, and which interoperates well with all of the other members of the same family. The circuits in your example may exhibit AND-like behavior in a stand-alone demo, but I think some of the answers below may be calling into question whether or not you could build a computer out of them. \$\endgroup\$ – Solomon Slow Nov 24 '20 at 17:05
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In the logic gate level digital design abstraction, inputs are assumed to switch from logic HIGH to logic LOW and vice-versa instantaneously. This is done to simplify logic design.

However, in the real world, it takes finite time to switch from one logic level to another. We want the time interval between switching from one logic level to another to be as low as possible.

It is also desired that the output of the digital circuit should not be sensitive to changes in the input unless the input is switched from one logic level to another. This is called noise immunity, and this gives digital circuits an advantage over analog circuits.

When designing digital circuits using transistors, in the CMOS technology, an NMOS transistor is used in the pull-down network and a PMOS transistor is used in the pull-up network. This is because NMOS is good at passing low voltage levels, but bad at passing high voltage levels. PMOS is good at passing high voltage levels, but bad at passing low voltage levels. We have to combine these 2 transistors in such a way that we are able to take advantage of the strengths of both type of transistors. This is done by using NMOS in the pull-down network since it can pass low voltage levels effectively and PMOS in the pull-up network since it can pass high voltage levels effectively.

Let us look at what happens if a PMOS transistor is used in the pull-down network and an NMOS transistor is used in the pull-up network. The threshold voltage of the NMOS transistor (IRF530) is 4 V and that of the PMOS transistor (IRF9530) is 3.3 V.

Bad buffer: NMOS in the pull-up network, PMOS in the pull-down network

schematic

simulate this circuit – Schematic created using CircuitLab

This is the DC Sweep characteristics of the above circuit, The X-axis represents the input voltage, which ranges from 0 V to 12 V. The Y-axis represents the output voltage.

Let us look at what happens when the input to this circuit switches from a logic LOW to logic HIGH. As can be seen in the below graph, this is not a good switching characteristic, since the output does not switch between 2 logic levels, instead it varies with the input, remains constant and then again varies with the input. Hence this transistor circuit is not suitable for digital circuits.

BAD_BUFFER_DC_SWEEP

Good inverter: NMOS in the pull-down network, PMOS in the pull-up network

schematic

simulate this circuit

This is the DC Sweep characteristics of the above circuit, The X-axis represents the input voltage, which ranges from 0 V to 12 V. The Y-axis represents the output voltage.

Let us look at what happens when the input to this circuit switches from a logic LOW to logic HIGH. From the graph below, it is observed that output is not sensitive to changes in the input, has a steep slope as it transitions from a HIGH level to a LOW level, and is not sensitive to changes in the input again. Hence it has a good switching characteristic and is suitable for digital circuits. The output is HIGH for a low input voltage and LOW for a high input voltage, since it is an inverter.

good_inverter_dc_SWEEP_characteristics

Good non-inverting buffer: 2 good inverters cascaded

schematic

simulate this circuit

This is the DC Sweep characteristics of the above circuit, The X-axis represents the input voltage, which ranges from 0 V to 12 V. The Y-axis represents the output voltage.

Let us look at what happens when the input to this circuit switches from a logic LOW to logic HIGH. From the graph, it can be observed that the output switches from LOW to HIGH, and the slope of the graph is steep, so this circuit has a good switching characteristic and is good for digital circuits.

good_buffer_characteristic

Conclusion

Now you know why you cannot design digital circuits with NMOS in the pull-up network and PMOS in the pull-down network. The AND gate circuit using 4 transistors uses PMOS in the pull-down network and NMOS in the pull-up network, hence it won't work effectively for the same reason that a buffer using PMOS in the pull-down and NMOS in the pull-up does not work effectively.

Further learning:

MIT OCW's excellent free online course on Computational Structures, which covers all topics from CMOS transistors to Parallel Processing.

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Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND (or NOR), and you need the two-transistor inverter to turn it into an AND (or OR).

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom; you need at least four transistors (two inverters) for that behaviour.

If you want to work out yourself with circuit analysis or whatnot for why it won't work, don't bother trying to do it with a NAND gate. Instead, do it for the non-inverting buffer with a NMOS on top and PMOS on the bottom. That will be sufficient for you to understand. You could even do it with a PMOS on the bottom and a pull-up resistor on top, or an NMOS on the top and a pull-down resistor on the bottom. Then note how your source voltage changes in the circuit as you try to turn transistors on and off, and remember that the gate-source voltage is what is controlling the MOSFET.

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So could anyone explain to me why an AND gate needs six transistors?

An AND gate does not need 6 transistors - this is because you're specifically referring to FCMOS (Fully Complementary MOS) where a PDN and PUN are completely complementary, as proven formally through De Morgan's laws. It can actually be shown there's no way to implement a NAND with just 1 PDN and PUN.

However, there are other logic families that give you better performance figures than FCMOS at the cost of others, allowing you for example to implement an AND gate with less than 6 transistors e.g. (D)CVSL and PTL. For example,

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ It looks like you are using an NMOS transistor for M6, which is the only transistor that can pull the output high. If that's the case then your output voltage will not reach the 3V that you assumed for your input voltage. Your example is non-restoring, so it doesn't look like a practical gate to me. \$\endgroup\$ – Elliot Alderson Nov 22 '20 at 21:13
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    \$\begingroup\$ @ElliotAlderson: That's true: a level restorer should be employed since at Vdd - Vtn (approximately) the NMOS will cut off. Depending on the application, this may be acceptable or not. As I noted in the answer, having fewer transistors does have costs. \$\endgroup\$ – edmz Nov 22 '20 at 21:33
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    \$\begingroup\$ Not being able to chain the gates means you cannot build arbitrary digital functions with such gates, which makes such schematic unusable as a logic family. It's the same as implementing an AND gate with two diodes: note there's no such thing as a "diode-diode logic". \$\endgroup\$ – Dmitry Grigoryev Nov 23 '20 at 10:40
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Here's a quick (and to me, easy to understand) answer, no equations needed.

Others have pointed out that Vgs is what controls nmos on/off state. If you try to use nmos as a pull-up element, the nfet ends up raising its own source voltage. If source voltage goes up, current goes down. It turns itself off!

This happens before the voltage reaches the supply. It happens slowly and gradually. So the output voltage will slowly approach some maximum value far below the supply voltage.

Same thing happens with pmos in the pull-down network.

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You could theoretically build an AND gate using the architecture complementary to the NAND gate, if you used depletion mode FETs. In practice, however, such a gate would not work with regular FETs as body diodes would short supply voltage to ground.

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Even if you manage to work around the body diode problem, you would presumably still need to build NAND gates with enhancement mode FETs on the same die, and the hassle of mixing enhancement and depletion FETs would certainly by far outweight the advantage of saving two FETs per AND gate.

Plus, nobody builds modern logic gates based on complementary depletion mode FETs, so the performance of such gates will most likely be worse than enhancement mode gates. Otherwise we would rather see depletion mode ICs everywhere, and the 4-FET NAND gate would be an oddity.

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A point not yet mentioned is that while a "stand-alone" AND gate would require six chips to implement in CMOS, incorporation of an "AND" function with other gates is often much cheaper. For example, if one wants to compute the inverse of (X or (Y and Z)), one could use a six-transistor AND gate along with a four-transistor NOR gate--ten transistors total. The whole circuit can be implemented much more cheaply, however, if one uses three PMOS transistors to pull up the output when X is false and either Y or Z is false, and three NMOS transistors to pull down the output when X is true or when Y and Z are both true--six transistors total.

Although there aren't standard logic symbols for gates that combine "and" and "or" functionality, it's not uncommon for a schematic to combine a large NAND gate with smaller "OR" gates directly attached to some inputs, or a large NOR gate with smaller AND gates. If all inputs are independent, such a gate will require two transistors per input, regardless of how AND and OR functions are combined, while using separately-constructed gates would require an additional four transistors for each AND or OR gate on the front end of a NAND or NOR (each such gate requires two transistors per input, but eliminate two transistors per input from the downstream gate, but would then need two transistors for the inverter, and two transistors in the next gate to receive the inverter's output).

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