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As far as I know in nmos the current flow from the drain to the source, and the drain and source are determined by the pin with the higher voltage on it (such that the source is the pin with the lower voltage). The bulk is always connected to the source so that the Vth won't change, however it appears that the source is the pin which is connected to the ground. Therefore my question is -

(1) how come does the current flow when Q2 is on, from the ground to Vsw? (2) Is it flowing from the source to the drain? how come? (3) And why not use a pmos instead, so that the current will flow from the source (the ground) to the drain (Vsw)?

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As far as I know in nmos the current flow from the drain to the source

That's not correct. Current can flow in either direction in an N channel MOSFET and, when the synchronizing MOSFET is activated, current flows from the right hand terminal of the inductor, through the load and output capacitor and up through the N channel MOSFET back to Vsw.

4 quadrant MOSFET VI curve: -

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Image from this website.

I believe that all your numbered questions are based on your initial misconception about MOSFETs.

The MOSFET drain to source connection is just a "resistive" channel - there's no PN junction involved in it at all so it will conduct just as well with a reverse current as a forward current. The only thing limiting full operation in reverse mode (bottom left quadrant) is the parasitic bulk diode whose effect you can see when Vgs is 0 volts - there is little negative conduction up until Vds becomes about -0.7 volts then, beyond that, it's a diode characteristic.

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  • \$\begingroup\$ Thanks, didn't know about the left plane side of the mosfet as you said; One question though - is the source and drain determined by the voltages in the circuit? or is it physically two different pins on the mosfet? (And where is the source and the drain in this specific circuit?) \$\endgroup\$
    – Jonathan
    Nov 24 '20 at 12:00
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    \$\begingroup\$ @Jonathan - the MOSFET drain to source is just a channel - there's no PN junction involved in it at all so it will conduct just as well with a reverse current as a forward current. The only thing limiting full operation in reverse mode (bottom left quadrant) is the parasitic bulk diode which you can see when Vgs is 0 volts - there is zero (or little neg conduction) up until Vds becomes about -0.7 volts then, beyond that, it's a diode characteristic. \$\endgroup\$
    – Andy aka
    Nov 24 '20 at 12:11
  • \$\begingroup\$ @Jonathan having second thoughts? \$\endgroup\$
    – Andy aka
    Nov 24 '20 at 12:49
  • \$\begingroup\$ Only about why dont use simply a pmos? is it because its more expensive & bigger for same current pushing? \$\endgroup\$
    – Jonathan
    Nov 24 '20 at 13:20
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    \$\begingroup\$ @Jonathan for a PMOS with its source at 0 volts you'd need a gate drive voltage below 0 volts to activate it but, then the parasitic bulk diode would always conduct and it wouldn't be feasible. With drain to 0 volts, to make it conduct (source connects to drain = 0 volts), then the gate drive voltage would still need to go below 0 volts and that is really inconvenient. PMOS isn't as fast or as highly conducting as NMOS for a given size. Pretty much everything you can think of will make PMOS a really bad choice. \$\endgroup\$
    – Andy aka
    Nov 24 '20 at 13:26
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how come does the current flow when Q2 is on, from the ground to Vsw?

Because of what you said earlier: "the drain and source are determined by the pin with the higher voltage".

In this circuit, you first turn on Q1, establishing a left-to-right current through L. Now, when you switch off Q1 and switch Q2 on, the voltage on the left end of the inductor will drop to below ground, so the upper end of the FET acts as the source and the lower end acts as the drain, and current continues to flow left to right.

The key thing going on is actually in the inductor, not the FET. Since the current through the inductor can't change instantaneously, and the right end of the inductor is at a (roughly) fixed voltage because of the output capacitor (whose voltage can only change slowly), the right end of the inductor must drop to a below-ground voltage to keep the current flowing. And the inductor uses its stored energy to "carry the current up-hill" from a low voltage to a high voltage, until either the next charging cycle starts (for continuous-current mode CCM), or the current drops to zero and Q2 is shut off (for discontinuous current mode DCM).

Is it flowing from the source to the drain?

It depends if you want to define the "source" and "drain" according to their nominal designations or according to how they function in the circuit at each instant. Really the FET doesn't care what you call its terminals --- if the gate is sufficiently positively biased, current will flow through the channel from whichever terminal is at a higher potential to the other terminal.

And why not use a pmos instead, so that the current will flow from the source (the ground) to the drain (Vsw)?

First, current already does flow from ground to Vsw in the circuit as it is.

With a PMOS, you'd have to drive the gate below ground (by at least a volt or two) to turn it "on" and this would be inconvenient.

Also, PMOS devices are typically less efficient than NMOS devices of the same size built in the same technology, because the hole mobility is lower than the electron mobility.

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Q2 serves the same job as a the flyback diode pointing up.

99.9% of all discrete MOSFETs have a parasitic body diode anti-parallel to the source-drain so can only block current in one direction.

Using a PMOS in that location would not work because of the parasitic body diode. It would just short to ground.

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