# Do I need more capacitance for my crystal?

I've used the formula "CL = (C1 * C2) / (C1 + C2) + Cstray" (where C1 = C2) to calculate the capacitors I need for my board. CL is 18pF, I ballparked Cstray at 5pF, meaning I should use 26pF capacitors. When I did so, I got this waveform:

Note that the center line is 0V, so this seems to have a good amount of swing above 0V, but then freaks out and doesn't go below it.

I don't feel like I understand the operation of this very well, and I'm trying to decide if this means I need more capacitance or less. Is this an expected waveform, or have I done something wrong?

• Don't discount the impact of your scope; often a modern oscillator won't even run if measured with a 1x probe, and a 10x probe isn't going to be without impact. It's possible that what you should really be measuring is the frequency accuracy and phase noise (neither of which are trivial to determine), and doing so from a derived or picked up signal, not directly, if you actually care. Otherwise things like reliable startup may be what is key. – Chris Stratton Nov 26 '20 at 5:16
• Which chip this is, and which crystal? Can you give make/model or links to datasheets? – Justme Nov 26 '20 at 5:17
• @ChrisStratton Good call, I don't know what type of probes I was using. I got a reading on another 16mhz crystal and it looked like a nice sin, though. – Helpful Nov 26 '20 at 5:36
• @Justme I'm making a 32u4 board, the crystal specifically is from digikey: digikey.com/en/products/detail/txc-corporation/9C-8.000MEEJ-T/… – Helpful Nov 26 '20 at 5:36
• @Helpful Atmega32U4, right? But which version of it, are there more details after U4? Anyway, 26pF is over the recommended limit of 22pF capacitors. And depending on which exact AVR model it is (i.e. which silicon revision, process and osacillator design version it has) the limit of total capacitance on pin is 22pF so capacitors should be much below 20pF. And, use 10x probes for measuring. – Justme Nov 26 '20 at 6:04

Some years ago I was accosted out in the engineering lab, and dragged over to stare at a scope.

The question was "Why is this Xtal oscillator amplitude larger than the simulation predicts?"

Given a number of issues and assumptions, and simulation nonlinearity behaviors, I was puzzled why a "precise amplitude" was expected.

However after a day or so, I realized the LOSSES within the ESD structures were not being simulated (and indeed likely were a bother for anyone to accurately measure, because the ESD clamping behavior is quite nonlinear and often very slewrate dependent), yet the ESD losses (at both ends of that PI matching/inverting 2_capacitor 1_Crystal circuit) might require MORE output power from the amplifier to overcome ESD losses.

And more output power requires LARGER voltage swings.

And larger voltage swings will trigger the ESD clamping behaviors.

Why is your waveform not moving below Ground?

• I, uh... have no idea. I'd guess based on what you're saying it's something to do with ESD clamping, but that seems pretty far beyond what I'm understanding right now. – Helpful Nov 26 '20 at 6:20
• Interesting story. Could you "connect the dots" so that the rest of us can understand what it has to do with answering the question? – JRE Nov 26 '20 at 9:22