I claim I can completely eliminate the quantization noise associated with the first-order single loop sigma-delta ADC. That is kind of overhyped but to me I have not been able to reject the claim yet. Mathematically it makes sense though. Anyway, here's my design:

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The equations for \$y_{1,i}\$ and \$y_{2,i}\$ can be written as $$y_{1,i}=x/2+\epsilon_i-\epsilon_{i-1}$$ $$y_{2,i}=x/2+\epsilon_{i-1}-\epsilon_{i}$$

The digital filters take average of the digital streams \$y_1\$ and \$y_2\$, hence \$D_{out1}\$ is the digital representation of the analog voltage \$y_1^{avg}\$ and \$D_{out2}\$ is the digital representation of the analog voltage \$y_2^{avg}\$. The voltages \$y_1^{avg}\$ and \$y_2^{avg}\$ are given as

$$y_1^{avg}=1/n\ \Sigma_{i=1}^{n}y_{1,i}=x/2+\epsilon_n/n $$ $$y_2^{avg}=1/n\ \Sigma_{i=1}^{n}y_{2,i}=x/2-\epsilon_n/n $$

where \$\epsilon_n\$ is the quantization noise for the last step. Now the analog voltage associated with the output Y, \$D_{out}\$, is simply $$ Y=y_1^{avg}+y_2^{avg}=x$$

So the quantization noise in the output code does not appear, and I have completely reconstructed the original input signal x. Am I right?

  • \$\begingroup\$ Try simulating it. \$\endgroup\$
    – Andy aka
    Commented Nov 26, 2020 at 19:17
  • \$\begingroup\$ the gain of the comparator should not be 1. \$\endgroup\$ Commented Nov 26, 2020 at 19:32
  • \$\begingroup\$ Of course it's possible. However, your scheme is parallel, it appears to rely at the very first block to have the gains of the two paths perfectly matched, which as you know is of course not possible. There are schemes that allow rejection of lower order noise up to any order in a series scheme, that doesn't need gain matching. \$\endgroup\$
    – Neil_UK
    Commented Nov 26, 2020 at 21:13
  • \$\begingroup\$ @Neil_UK So do you agree that in an ideal case I could have reproduced the input signal to whatever resolution I wanted? Because the addition of y1 and y2 should give the accurate result to within a certain number of bits, which could ideally be infinite \$\endgroup\$
    – dirac16
    Commented Nov 27, 2020 at 8:18

1 Answer 1


First, the 1/2 factor at the input is superfluous; it has no useful function. Second, you seem to have an ADC that is able to reproduce an exact version of its input signal. This is not possible since an ADC only has a finite number of output values while the input analog signal can have an infinite number of values since it is a continuous function. This means that different input signals can map to the same ADC output due to the finite quantization of the ADC. Thus once you have done an ADC conversion, you have lost some information about the input signal. Therefore you cannot reproduce it exactly at the output. Therefore I believe there is a fundamental flaw in your design. As suggested by Andy, try simulating it and see what happens especially with different types of input signals: sine, square and triangle.

  • \$\begingroup\$ Yes, I agree. However there is a thing. Say both structures are designed to resolve 16bits. But I enlarge the output code registers to 20bits, now the final output is accurate within 20bits, am I right? \$\endgroup\$
    – dirac16
    Commented Nov 27, 2020 at 8:07

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