# FSM binary number divisible by 5 truth table

I am having trouble seeing if my truth table based on the exercise's instructions is correct (mostly because the instructions are really confusing me and the TA's explanation really didn't help, this is kind of my last resort).

Instructions:

Consider a circuit that has a data input Data and a reset input Reset and a single output Z. The output Z should be asserted true (set to 1) whenever the string of 1s and 0s entered since the last assertion of Reset, when interpreted as an unsigned binary integer, is divisible by 5. Otherwise it should be set to false (0). Assume that the two inputs act independently, i.e., they can change at the same time. Also, approach this problem using a Moore machine, where the output Z’s value is associated with being in a particular state, and not with the transition itself. This will be explained further in class - the parity-checker FSM is an example of a Moore machine. Finally, use the following properties:

1. If a%5=α and b%5=β then (a+b)%5=(α+β)%5.
2. If a current string has a numerical value of x then placing a 0 on the right hand side results in a string having a value x + x and placing a 1 results in a string having a value x+x+1.

UPDATE (more instructions that the professor has relayed now):Derive a symbolic state transition table for this problem (a finite state machine). Now, choose a state encoding and then, using D flip-flops that are rising-edge triggered, derive expressions for the output Z and the new states as functions of the current states and the current inputs.

This is the truth table that I came up with:

Q2   Q1  Q0  D R |  Q2' Q1' Q0' Z
0    0    0  0 0 |  0   0   0   1
1 0 |  0   0   1   0
0 1 |  0   0   1   0
1 1 |  X   X   X   X

0    0    1  0 0 |  0   0   1   0
1 0 |  1   1   0   0
0 1 |  1   1   0   0
1 1 |  X   X   X   X

0    1    0  0 0 |  1   0   0   0
1 0 |  0   0   0   1
0 1 |  0   0   0   1
1 1 |  X   X   X   X

0    1    1  0 0 |  0   0   1   0
1 0 |  0   1   0   0
0 1 |  0   1   0   0
1 1 |  X   X   X   X

1    0    0  0 0 |  0   1   1   0
1 0 |  1   0   0   0
0 1 |  1   0   0   0
1 1 |  X   X   X   X


where Q2,Q1,Q0 represent the remainder present state in binary form and Q2',Q1',Q0' represent the remainder next state in binary form. Inputs: D=Data, R=Reset. Outputs: Z (The X represents some next state that isn't important (from what I understood of the instructions) since D and R are independent.

• Why do you assign x to Qx' if both inputs are set? And why does the reminder change in some cases if D=0? And wouldn't the only state that would lead to Z=1 be if the current reminder is 1 0 0 and D=1? Commented Nov 27, 2020 at 7:44
• From my understand, if both inputs are 1, then it doesn't matter. But, I am really confused about the instructions, which is why I am asking for help to verify whether or not my truth table is correct. Commented Nov 27, 2020 at 18:40
• It seems like this problem statement is missing something, such as the clock to trigger sampling of the input data. In a practical sense of coping with a defective assignment, your greatest practical clue is probably the parity FSM they mention; effectively you can consider this thing an evolution of that thing, so whatever the official solution for that is will probably inform the shape of the expected solution for this. It's a pity teachers aren't more careful to state solid problems, however. Commented Nov 27, 2020 at 18:41
• @ChrisStratton Yeah, they just mentioned in the class forum that it is supposed to be a rising-edge triggered D flip-flop Commented Nov 27, 2020 at 19:02

I would not interpret independent as exclusive and not have don't cares in the state transition.
I think it unspecified whether Data in/at a/the cycle Reset is asserted is included in the number. (New number starting in "reset cycle" or in cycle following reset: I prefer following - consider back-to-back reset cycles.)
1 1 0/6 is not a useful next state to specify when you don't include it in the set of current states handled.
• The non-reset handling looks right but for 0 0 1: the new remainder should be 2 or 3.
• I do not understand why the next state with Data 0 and Reset asserted would be the same as no reset and Data 1.

My take (personally preferred/alternative states where different):

Q2   Q1  Q0  D R |  Q2' Q1' Q0'   Z
0    0    0  0 0 |  0   0   0     1
1 0 |  0   0   1     0
0 1 |  0   0   0     1
1 1 |  0   0 0/1   1/0

0    0    1  0 0 |  0   1   0     0
1 0 |  0   1   1     0
0 1 |  0   0   0     1
1 1 |  0   0 0/1   1/0

0    1    0  0 0 |  1   0   0     0
1 0 |  0   0   0     1
0 1 |  0   0   0     1
1 1 |  0   0 0/1   1/0

0    1    1  0 0 |  0   0   1     0
1 0 |  0   1   0     0
0 1 |  0   0   0     1
1 1 |  0   0 0/1   1/0

1    0    0  0 0 |  0   1   1     0
1 0 |  1   0   0     0
0 1 |  0   0   0     1
1 1 |  0   0 0/1   1/0