# Low impedance complementary negative level shifter for a BBD

I'm trying to clock a BBD (Bucket Brigade Device) circuit (for example the MN3007) from a microcontroller output. However, the circuit requires a complementary negative clock, i.e. CP1 is $$\-12V\$$ to $$\0V\$$ and CP2 is $$\0V\$$ to $$\-12V\$$ (for $$\\mathrm{VDD} = -12V\$$). The transition time for the clock is specified as less than 500ns, although I'd prefer to be well below that since apparently the clock signal directly drives the BBD transistors, so a slow transition increases non-linearities. Further, apparently the output should have reasonably low impedance, as the clock IC usually used with these types of BBD's (such as the MN3101) advertises about $$\2mA\$$ output current. Yet worse, the datasheet specifies that the clock cross point, i.e. where the the two complementary clock signals cross, should be between 0V and -3V, so a perfectly symmetrical drive won't do. One last technical requirement is that the that the clock voltages should be as close as possible to the rails, since those limit the signal swing (looking at the datasheet, the clock directly drives the gates of the switching transistors).

So, to summarize, your mission, should you choose to accept it, is to

point me to the right direction for designing a circuit that:

1. Given an input clock signal 0V - 3.3V, generates a complementary pair of clock outputs with levels 0 and -12V
2. transition time is less than 500ns
3. The clock outputs are able to provide at least 2 mA of output current
4. The levels are as close as possible to the rails (this disqualifies the most standard BJT circuit, such as discussed in this question)
5. The clock signals cross between 0 and -3V: alternatively: instead of providing the complementary outputs, I'll just design a good level shifter, and I'll use two channels of MCU PWM outputs for the complementary clocks and time them to adjust the crossing level. This requires that the level shifter edge shape is predictable in production and over varying environmental circumstances.
6. Price is important, 1\$ per clock is already a lot (I'll be needing two of these per device, production numbers will probably be in the hundreds so parts pricing at hundreds is the correct quantity to consider)
7. PCB real estate is even more important

Bonus goals:

1. Using only components that can be wave soldered (due to some inevitable through hole components, we have to wave solder one side of the board, so this would give me a chance to keep all components on one side), while still keeping 5. and 6. in mind.
2. Transition time is much less than 500ns.

Possible trick to use:

One way that could make life a bit easier is that I could just as well hang the BBD between the +12V and 0V rails, instead of 0 and -12V. This would mean that the clock levels would instead be +12V and 0V, and the crossing point would be between +12V and +9V.

Let me post one answer which I figured out. This is reasonable, but not perfect yet: simulate this circuit – Schematic created using CircuitLab

So this is really just a reasonably trivial implementation with a comparator, and using the TSX3704 quad, the cost is about 35 cents + 4 resistors per clock (the thresholds for the comparators can be shared... actually I can save one further resistor by sharing the voltage divider string for the two voltages shown, so 3.5 resistors per clock). Further, I have a choice of the SOIC-14 package which is huge but wave solderable, or something smaller if I fail to keep everything one sided.

So how do I fare against my own criteria:

1. Check
2. Check
3. Check
4. Reasonably good, less than 200mV from the rails, and if I'm reading Figures 8. and 10. in the datasheet correctly, essentially zero once the gates have been charged. Indeed, using an even cheaper TS3704 might also be possible, although it's datasheet doesn't show the corresponding plots.
5. The slight difference between the trip points takes care of this
6. Not bad, less than 40 cents total per clock.
7. I get to choose between this and bonus goal 1

Bonus goals:

1. I get to choose a compromise between this and 7.
2. Check

I'm still interested in other solutions, I wonder if there's still some room to improve on the parts count/cost and especially the size of the very big SOIC-14. Maybe at the expense of the transition time which is now over spec by about a factor of 50.

• Your circuit looks good and cheap – unlikely to get any cheaper! The timing is very touchy and may need a tweak... You want the hi-to-lo comparator to start its transition only after lo-to-hi comparator reaches its final 3V? Datasheet implies that may be in the neighborhood of 10ns (but you’ll have to measure it, and hope it’s steady across lots of units). So your clock delay has to be around 10ns, but your circuit won’t do that: it’s delay is merely the time it takes your 3.3V clock source to get from one comparator threshold to the other, probably about 1ns. Nov 30, 2020 at 4:12