BJT Saturation Design Point?

Question

I was reading an answer to this other question which asks about saturation of a BJT transistor.

In that answer it states to be saturated you should shoot for a 1:10 ratio or more between base current and collector current. While this is perfectly acceptable, the MMBT5087 transistor meantioned in that question specifies a minimum hFE value of ~150.

In theory the base current can be reduced until it's just bigger than a 1:hFE ratio with the collector current. However, for practical designs I would assume designing close to the 1:150 ratio is risky, even if this is the specified minimum value (if I'm reading the datasheet right).

My question is what type of safety factoring should I aim for (assuming I want to minimize base current)? A 1:10 ratio seems a bit excessive as that provides a FOS of 15. Also, this specific example is a PNP type transistor. Are there any different recommendations for NPN type transistors?

Answer 1

Read the datasheet more closely : there will be conditions attached to that spec for a minimum hFE. One of those conditions will be that Vce is greater than some voltage : probably 2V. (Just checked the datasheet; actually Vce=5V). When you are trying to saturate the transistor, those conditions obviously no longer apply. Instead, as Vce approaches Vce(sat) hFE decreases quite dramatically.

Note that the actual base current and hFE will vary for Vce(sat) - you might find hFE=25 at that point for a particular transistor and a particular current Ic, or alternatively at hFE=10 you might see Vce lower than the rated Vce(sat) - the datasheet Figure 2 shows Vce(sat) around 0.05V for a useful range of currents! But these are the figures guaranteed by the makers for all their transistors.

Answer 2

You do not want to design saturated switching circuits that depend too closely on the actual value of the transistor hFE. The value you saw for ~150 can vary over quite a range from part to part.

I would design such circuit to operate with an assumed hFE minimum of say 50. That would give you a nice margin from the specified minimum value for the transistor and still keep the transistor base current relatively small with respect to the collector current.

The guidelines for PNP transistors and NPN transistors will be basically the same with regard to how to judge the design margin for the hFE minimum value.