# System Verilog code syntax error

I wrote the following code:

module mul3 (
input logic[1:0] d
);
mul3_op[0]=d[0];
endmodule;


But when I run it using Modelsim I get the following messages:

Error: (vlog-13069) mul3.sv(21): near "[": syntax error, unexpected '['.

Error: mul3.sv(21): (vlog-13205) Syntax error found in the scope following 'mul3_op'. Is there a missing '::'?

Please note that line 21 is actually the last line before endmodule in the code above. Any idea of what is wrong?

• Mybe "input logic[1:0] d," and "output logic[3:0] res" should be "input [1:0]logic d," and "output [3:0]logic res". Nov 27 '20 at 12:24
• @Arseniy what I wrote is correct; input appears before Nov 27 '20 at 12:27
• You missed 'assign' before that statement. Nov 27 '20 at 12:35
• why I need assign? Nov 27 '20 at 12:37
• Because that's the standard syntax. Nov 27 '20 at 12:37

assign mul3_op[0] = d [0] ;