0
\$\begingroup\$

I wrote the following code:

module mul3 (
    input logic[1:0] d
);
mul3_op[0]=d[0];
endmodule;

But when I run it using Modelsim I get the following messages:

Error: (vlog-13069) mul3.sv(21): near "[": syntax error, unexpected '['.

Error: mul3.sv(21): (vlog-13205) Syntax error found in the scope following 'mul3_op'. Is there a missing '::'?

Please note that line 21 is actually the last line before endmodule in the code above. Any idea of what is wrong?

\$\endgroup\$
6
  • \$\begingroup\$ Mybe "input logic[1:0] d," and "output logic[3:0] res" should be "input [1:0]logic d," and "output [3:0]logic res". \$\endgroup\$
    – Arseniy
    Nov 27 '20 at 12:24
  • \$\begingroup\$ @Arseniy what I wrote is correct; input appears before \$\endgroup\$ Nov 27 '20 at 12:27
  • 1
    \$\begingroup\$ You missed 'assign' before that statement. \$\endgroup\$
    – Mitu Raj
    Nov 27 '20 at 12:35
  • \$\begingroup\$ why I need assign? \$\endgroup\$ Nov 27 '20 at 12:37
  • 1
    \$\begingroup\$ Because that's the standard syntax. \$\endgroup\$
    – Mitu Raj
    Nov 27 '20 at 12:37
2
\$\begingroup\$

You missed assign keyword for that concurrent statement -

assign mul3_op[0] = d [0] ;
\$\endgroup\$
3
  • \$\begingroup\$ Do I need assign too if I wrote: "mul_enable[1]=mul;" \$\endgroup\$ Nov 27 '20 at 12:42
  • 1
    \$\begingroup\$ Any assignment outside the always block need the "assign" word. \$\endgroup\$
    – Arseniy
    Nov 27 '20 at 12:46
  • 2
    \$\begingroup\$ Yes if it's a continuous assignment, ie., outside always/initial blocks. \$\endgroup\$
    – Mitu Raj
    Nov 27 '20 at 12:47

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.