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I have come across material per review from my past encounters with digital sequential logic and I wanted to pose a specific and hopefully general question for the community to help shed some light.

I have found reference to the term "transparent" latch and I discovered that it permits the output to get the input to flow through the output of the latch.

However per my understanding I see that use of a latch (specifically "transparent") is discouraged in digital design, specifically sequential providing any sort of clock should not be used in this process.

What is the effective disadvantage of using a latch instead of a flip flop, and where are they effectively used?

Why is the left good, and the right is bad?

Diagram

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  • \$\begingroup\$ Did you Google first? \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 14:57
  • \$\begingroup\$ @DKNguyen, I will revise my question to indicate my current understanding, add details and hope not to branch into too many directions. Sometimes, switching between fields makes it difficult to assess the level of detail I need in my question \$\endgroup\$
    – Vahe
    Commented Nov 27, 2020 at 14:59
  • \$\begingroup\$ We expect you to do some research and then ask a question that addresses what you are having difficulty with. A quick search reveals numerous excellent answers to this question. \$\endgroup\$ Commented Nov 27, 2020 at 14:59
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    \$\begingroup\$ Much better....... \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 15:11
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    \$\begingroup\$ You should update the question title as well. \$\endgroup\$
    – Finbarr
    Commented Nov 27, 2020 at 15:14

2 Answers 2

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To understand why an unclocked component of any kind is discouraged in sequential digital design you need to understand why a clock exists in the first place.

The clock keeps things in synch and makes it easier to design for. With no clock you have to rely on the delay between components matching up with each other so signals arrive at their next destinations neither too early nor too late (i.e. at exactly the right time). With thousands of branches and paths that are always changing, this is really difficult for very large circuits.

With a clock, everything just needs to arrive at its destination faster than the clock.

Since a transparent latch is not clocked, it is a bit of a renegade when using it amongst clocked components since it can allow signals to change when the clocked components are not expecting it. You can get away with it sometimes at the input or output of a system where things are more predictable, but in the middle of a system is often no good. It's about manageability of the timing. If part of the system is simple enough so you know what is going to happen, you can get away with it.

In FPGAs, specifically, transparent latches are discouraged because their timing is uncontrolled and FPGA architecture does not support them well so it produces unpredictable results.

Latches are a form of memory, be definition, and combinatorial circuits do not have memory by definition. But you can have simpler, unclocked, sequential circuits where the timing is more manageable. That's where transparent latches can be useful.

They are also useful to shield noise between circuits like ADCs, but that isn't digital logic design.

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  • \$\begingroup\$ Please elaborate why the use of latch in this case is not encouraged, is there a specific disadvantage, and advantage in generic logic design? \$\endgroup\$
    – Vahe
    Commented Nov 27, 2020 at 15:19
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    \$\begingroup\$ @Vahe Generic logic design doesn't have much meaning. \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 15:24
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    \$\begingroup\$ @vahe In an clocked circuit, everything needs to arrive before the clock. Much faster doesn't matter as long as it is ready when the clock arrives. But in an unclocked circuit everything must arrive at EXACTLY the right time. Arrive too soon or too late and things break. \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 15:32
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    \$\begingroup\$ Combinatorial circuits have no memory so have no latches. There is combinatorial (no memory) vs sequential (memory) and clocked vs unclocked. There are 4 possible combinations. It is not as much of a problem with combinatorial due to no memory, but if you have something big and feeding it really fast it can become a problem. \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 15:36
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    \$\begingroup\$ You just don't want the pins of the ADC wiggling when the comms are not to the ADC. There are multiple ways to fix the value at ADC pins during this time. Transparent latch is one. OR is another. \$\endgroup\$
    – DKNguyen
    Commented Nov 27, 2020 at 15:45
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In synchronous logic (particularly within FPGAs), the use of asynchronous parts (of which the transparent latch is but one) makes no sense, but there is a real use case for transparent latches even in a clocked system.

The venerable XX373 8 (and 16) bit transparent latch is a very common choice for address buffers in microprocessor based circuits, for example.

Many of those microprocessors also multiplex address and data; this is often the lower order part of the data bus but I have seen where the entire address / data paths are multiplexed - this saves physical pins and continues to this day for parallel interface memory subsystems.

We latch the address bus on an event known as ALE (Address Latch Enable) and the timing is often quite critical. This then maintains this address data for the remainder of the memory access cycle. The pins that were the address bus at the start of the cycle are now data bus bits.

See this page for a decent example.

Now consider a signal that will be gated by some external event and we do not know when that event will occur. This can be handled in synchronous logic but requires the use of 2 flip flops and a relatively fast clock (to synchronise the signal to the clock). A transparent latch is a good fit for this case where the clock rate may be slow compared to the event itself.

So neither is better or worse; it all depends on the use case.

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  • \$\begingroup\$ Why is a transparent latch considered an asynchronous element? Does this extend to non transparent latch? \$\endgroup\$
    – Vahe
    Commented Nov 27, 2020 at 16:17
  • \$\begingroup\$ A synchronous latch clocks data through on a clock. A transparent latch freezes data at the output when the enable is made false which may be a clocked signal but will not be the main clock itself. \$\endgroup\$ Commented Nov 27, 2020 at 16:23
  • \$\begingroup\$ Is what you are describing clock gating? \$\endgroup\$
    – Vahe
    Commented Nov 27, 2020 at 16:58

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