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When the 8088 goes into hold, every output is tri-stated apart from HLDA (obviously), ALE and INTA. Given that the purpose of hold is to allow an external device to control the bus, like a DMA controller, what's the rationale behind ALE and INTA still being driven?

I think I partly know the answer to this:

If INTA (which normally isn't connected to another bus controller) wasn't driven high, it might float low and accidentally cause an interrupt vector to be placed onto the data bus causing contention.

If ALE wasn't driven low, it might float high and accidentally latch some spurious low-order address data, so that when the CPU came out of hold then A0..A7 would be incorrect. But this wouldn't matter, would it? As after exiting hold the next instruction's T1 cycle would cause the correct low-order address lines to be latched.

Is it simply that ALE doesn't NEED to be tri-stated?

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Indeed, bus ownership is the key here. Asserting INTA grants an external device permission to drive the bus, but since the CPU is not allowed to drive the bus at this point, it is also not allowed to delegate that permission.

ALE goes to a single external component that we don't want to glitch -- it's not a bidirectional signal, and tri-stating it would only require adding a pull-down resistor.

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  • \$\begingroup\$ Thanks. Can you explain your point "tri-stating it would only require adding a pull-down resistor"? ALE is driven low in hold, isn't it? My question is why didn't Intel tri-state it in hold along will the address bus? \$\endgroup\$
    – David00
    Nov 27 '20 at 20:04
  • \$\begingroup\$ @David00: Because, as Simon said, if ALE were tristated, you would then need an external pulldown resistor to hold the signal low. The address latch is dedicated to the CPU, and is not intended to be shared with other bus masters. \$\endgroup\$
    – Dave Tweed
    Nov 27 '20 at 20:27
  • \$\begingroup\$ @Dave Tweed: Ah, I can see why my response didn’t make sense. Whether ALE is tri-stated or pulled low doesn’t really matter. ALE is enabling (or not enabling) data into a latch, but when the CPU is in hold and not in control of the bus, something has to disable the output of that latch which otherwise would still be driving the address bus. Typically HLDA would be connected to the latch’s OE input for this purpose. \$\endgroup\$
    – David00
    Nov 27 '20 at 22:49
  • \$\begingroup\$ @ Dave Tweed: If the latch output is disabled, and therefore not on the bus, why did Intel choose to leave ALE active? I suspect it’s because ALE at that point, whether active or tri-stated, isn’t affecting the output of the latch. Which is why I’m guessing that Intel didn’t use a 3-state driver, so as to save some die space. Does this make sense? \$\endgroup\$
    – David00
    Nov 27 '20 at 22:49
  • \$\begingroup\$ I doubt whether die space had anything to do with it. There was simply no reason to tristate ALE, so they didn't bother. \$\endgroup\$
    – Dave Tweed
    Nov 28 '20 at 0:16

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