I'm new to electronics in general so please don't assume any prior knowledge. I'm developing a control board and I've already had the first revision manufactured. Everything worked as expected with the exception that I had crosstalk from my SCK line to my MISO line on 5 boards out of 5 which was severe enough to ruin the SPI communication. Just for the record, I've successfully set up various configurations of these units on a breadboard, but with fewer components.

The setup is the following (only including SPI-relevant components):

The first design had terrible routing where I had done the following:

  • Star topology
  • All SPI traces very close in parallel at the limit of the manufacturing house specifications
  • Excess of vias since I routed the SPI last, instead of in the beginning
  • Although catastrophic layout, the rise time for the SCK was <2 ns.

In this second revision I'm starting fresh and I've done the following:

  • Routing the SPI first
  • Serial topology (that's what it's called, right?)
  • Track width: 5 mils
  • Min SPI track spacing: 10 mils (ca. 15 mils most of the board)
  • Going for a higher-end manufacturing house than last time
  • No vias for SCK line, attempting to minimize vias for MOSI and MISO (this is my issue)
  • The tracks are ca. 15 inch (380 mm) each

Now for my questions:

  1. I still feel that my routing looks very beginner-like and with more vias than necessary. Do you have any suggestions?
  2. I'm only putting traces on layer 1 and 4, should I consider routing some SPI traces on for example the power layer by clearing out some area? By using long traces in parallel on both L1 and L4, it'll be difficult to cross the path with all the other remaining traces.
  3. Should I worry about any termination in this case?
  4. I've got plenty of Tee-crossings, how does one avoid those 90 degree angles?
  5. Any other tips that could be useful for this project or future ones?

Due to other design considerations, I cannot move the components closer together unfortunately.

Draft SPI layout

This is my first post, so I hope I've included everything that's relevant.



Thanks for the questions so far.

There are 10k pull-up resistors on the CS close to the ICs; on the PCB or on the the break-out boards. No other pull-up, pull-down or series resistors.

I just went to get some additional measurements for this thread, but now I'm more confused than before. I'm not able to catch any measurements using the Arduino SPI functions as it instantly freezes when connected to any of the PCBs. I made these measurements with no SPI-related components soldered/connected to the board. Below are two sets of measurements using DigitalWrite() on the SCK pin, or AnalogWrite(). I notice that AnalogWrite has good signal integrity while the DigitalWrite looks horrible.

Here's a few photos of the scope... SCK pin with AnalogWrite(SCK_Pin, 1) SCK pin with AnalogWrite(SCK_Pin, 1)

MISO pin with AnalogWrite(SCK_Pin, 1) MISO pin with AnalogWrite(SCK_Pin, 1)

SCK pin with DigitalWrite, high for 1 us, low for 10 us. High 1 us, low 10 us

Now, what I find really weird is that even when the Teensy is unplugged from the PCB, the signal integrity is really poor using DigitalWrite as compared to AnalogWrite. The PWM frequency for that particular pin on the Teensy is 3.611 kHz by the way.

DigitalWrite() with Teensy off-board DigitalWrite() with Teensy off-board

  • 1
    \$\begingroup\$ What does severe mean? Note that on many chips the MISO line is undriven until the chip actually sends data out, so it simply could be nothing driving it. Are there any series resistors or pull-ups/pull-downs on the SPI lines? Also show the schematics, maybe there is just missing decoupling or something. \$\endgroup\$
    – Justme
    Commented Nov 27, 2020 at 22:14
  • \$\begingroup\$ Can you show us the crosstalk on a scope plot? Are you sure it isn't noise from the stepper motor drivers causing the issue? Does the issue happen without the stepper motors connected? \$\endgroup\$
    – Mattman944
    Commented Nov 28, 2020 at 0:10
  • \$\begingroup\$ I couldn't put the link to the schematic in the original post due to low reputation. Is there any easy way to export from KiCad to the forum drawing app? Here's a link to a pdf of my schematic: dropbox.com/s/caddrjovzejckdc/Integrated_PCB_Rev2_1.pdf?dl=0 I'm not familiar with the conventions and standards of producing these, so I'm sorry if they're not up to standard. Is there a way of uploading a schematic without having to redraw it in the app of the forum? \$\endgroup\$
    – Victor
    Commented Nov 28, 2020 at 2:35
  • \$\begingroup\$ Regarding the stepper motor drivers. I haven't even started using them on this PCB since I haven't even gotten the SPI communication to work yet. Just FYI: I've made another PCB (my first one, prior to attempting this more comprehensive project) where they worked perfectly. \$\endgroup\$
    – Victor
    Commented Nov 28, 2020 at 2:38

2 Answers 2


This doesn't look to bad. It would be important to know the SPI CLK frequency. First try to reduce the frequency of the SPI Bus to see if you your problem is getting less sever.

My first guess would be rather some pins that are not set correctly or wired wrong. If you can try removing a slave at a time and see if that solves your problem. With the attached picture it is quite hard to give advise. If you can share the board file you are more likely to get some help.


I know this is an old post but I had similar (noise / Crosstalk / signal integrity) issues with 12 SPI devices in my project (20MHz clock). This is how I solved the issues:

  1. I have used fan-out buffers on clock and data and series termination resistors on each transmission line.
  2. For MISO I have used star connection topology and tied all 12 MISO lines at master MISO pin.
  3. I used a ground via close to a signal via anytime a data / clock trace switches PCB sides.
  4. I have used 4 layer PCB with the following stack-up : Signal/Power Top / Ground / Ground / Signal/Power Bottom. I have stitched two inner ground planes with may vias. This way my signal traces always have a reference ground plane right underneath them which improves signal integrity and reduces noise and crosstalk. I routed power on top and bottom layers using power copper pours anywhere I could and stitched them together with many vias.
  5. I used low ESR bypass capacitors and placed them very close to chip's power inputs.

Hopefully this helps.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.