# Capacitor for triggering negative edge J-K Flip Flop's Clock

I have some SN74LS73AN Flip-Flops which, if I understanding well, are triggered by the negative (falling) edge signal of a clock. I wish to use a simple pushbutton as a clock, and I am aware that, for a clean (debounced) clock signal, a capacitor is needed. I'm using a 5v DC powered breadboard and a SN74LS73AN J-F Flip Flop. What kind of capacitor should I get? Thank you.

• You don't need a capacitor to generate a negative or positive edged clock hence, your question is flawed. Nov 28, 2020 at 15:34

"Negative edge" doesn't mean a negative voltage. A negative voltage is a bad thing for most digital circuits.

"Negative edge" means the falling edge of the clock pulse. That is, the transition from high to low.

This is a negative edge:

That's a 1kHz square wave. It varies between 0 and 4V at 1kHz.

You don't need a capacitor to make a negative edge. You just need to make a falling edge.

You make a falling edge like this:

simulate this circuit – Schematic created using CircuitLab

When you push the button, the clock goes from high to low. When you release the button, the clock goes from low to high.

There's just one problem with that.

Buttons don't switch cleanly. When you push the button in a real circuit, the clock will look like this:

Over to the left, the output starts out high. The button is pressed, and the contacts bounce several times before the output finally goes low and stays there over at the right side.

Every zig-zag is another pulse for the J-K clock input. Pushing the button once will generate a whole bunch of clock pulse instead of just the one you want.

If you were using a microcontroller, you would write a simple debouncing routine to ignore the short pulses.

Since you are using a 7473, you'll have to debounce the switch in hardware - and here at last you will need a capacitor.

To debounce the button, you would modify the circuit like this:

simulate this circuit

With the additional resistor and the capacitor, the falling edge looks like this:

The clock drops fast over on the left edge on the first contact. The capacitor and the resistors prevent it from rising on the bounces. Over to the right, the pulse is completed.

You'll get one pulse on each press of the button just like you wanted.

R1 is a pull up resistor. It holds the clock signal high all the time.

C1 is there to remove the bounces. Together with R1, C1 forms a low pass filter with a time constant of about 10 milliseconds. Anything that "moves faster" than that gets filtered out. The bounce in the first button circuit was over after about 1.5 milliseconds. The 10 millisecond time constant is slow enough to remove those fast bounces.

R2 is there to limit the discharge current from the capacitor. A dead short circuit of a capacitor can cause a lot of current to flow. 100 ohms is low enough to quickly discharge the capacitor, but still not be a dead short circuit.

• Thank you very much! that's what I was looking for. I will try it as soon as I get some 100nF capacitors. Greetings. Nov 28, 2020 at 18:30
• If I understand, if I decrease the resistance of the circuit I could use a bigger capacitor. If that's correct, what resistors should I use for being able to use a 100μF capacitor? Nov 28, 2020 at 19:41
• 100µF is way too big. You would need for R1 to be about 100 ohms, which would mean you'd have to make R2 much smaller. That's not a good idea. The current from the 100µF capacitor stands a good chance of welding your switch contacts together if you leave out R2 or make it too small.
– JRE
Nov 28, 2020 at 19:44
• A 1µF capacitor and 10k for R1 is about as big as I'd go on the capacitor.
– JRE
Nov 28, 2020 at 19:44
• The edges from these circuits are going to be too slow for the 'LS73 to clock properly. You need to run this through a Schmitt trigger in order to get the edge speed down to the 10 ns or 20 ns range before going into the clock input of the FF. Nov 28, 2020 at 20:06

If you asking about creating a short negative-going pulse from a switch output, then what you want is a capacitor in series between the switch and the clock input. This circuit is a differentiator. Can't do a schematic right now, so here is some text.

The circuit is the switch to GND with a resistor to Vcc, the series capacitor to the ff input, and a resistor from the ff input to Vcc. The width of the pulse that the ff sees is based on the R-C time constant of the capacitor and the pullup resistor at the ff input. The effective pulse width is close to 1 x R x C because the ff input transition level is close to 37% (1/e) of Vcc. Start with the desired pulse width, choose the pull up resistor value based on circuit conditions (a very large resistor reduces the capacitor size, but makes the circuit more susceptible to noise, etc.), and then calculate the capacitor value.

A typical R value for an LSTTL circuit might be 4.7K. If you want a pulse width of 10 ms, then C equals 2.2 uF - ish.