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hi I didn't studies all the circuit configurations and also I'm a newbie to EE. My question is I need to design something like a voltage holder.

The idea is two emitter followers. One is NPN one and other is PNP one and it will balance the threshold voltage across junctions. Circuit diagram looks like this. enter image description here

The functional requirement is that when I press the 5V switch , the outuput voltage should go to 5V and hold it 5V no matter I released the switch. And when I give a 2V pluse , it should again come back to 2V.

The problem is, circuit simulator does not output it's expected functionality. Any reasons why is that? It came back to OV, and sometimes it give me a convergent error.Any workaround on this?

--Thanks in Advance--

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    \$\begingroup\$ Perhaps the term of relevance is sample & hold circuit... \$\endgroup\$ – Anindo Ghosh Jan 9 '13 at 10:00
  • \$\begingroup\$ Is there are already researched circuit configuration like this? \$\endgroup\$ – Standard Sandun Jan 9 '13 at 10:02
  • \$\begingroup\$ @AnindoGhosh feel free to edit it. Or I will edit it, that term is nice. \$\endgroup\$ – Standard Sandun Jan 9 '13 at 10:03
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    \$\begingroup\$ Please see this patent, it's probably useful towards what you are trying. \$\endgroup\$ – Anindo Ghosh Jan 9 '13 at 10:05
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    \$\begingroup\$ @sandundhammika You don't need others to close a question, you can remove it yourself. Also, no credit needed, but thanks for the thought. :-) \$\endgroup\$ – Anindo Ghosh Jan 9 '13 at 10:09
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What you're talking about is called sample-and-hold. To do this, you need a storage element - a circuit without one like yours will rapidly drift. The most common way to do this is to use an Op-amp:

enter image description here

The two triangles represent op-amps configured as voltage followers. The first one acts to decrease the impedance of the input, allowing the capacitor to be charged faster; in your example diagram this isn't necessary since your input is already low impedance. The second opamp provides a low impedance output, making it possible to interface the sampled voltage with other parts of the circuit without draining the capacitor.

Even with a circuit like this, you need to recharge the capacitor periodically, as it will gradually discharge due to parasitic resistance. In a digital system this would typically be implemented with a DAC and a multiplexer controlling the sample switch, which loops through each sample-and-hold output in order, refreshing them periodically.

You can also get dedicated sample-and-hold ICs that integrate the opamps and switch, and have very low droop rates, but they tend to be expensive and specialized.

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  1. As Nick said, a sample and hold circuit inherently needs some kind of storage or memory. You have none. For starters, put a large cap to ground on the base of Q1. That will hold the voltage for some time for some level of close enough. You said nothing about how long the desired voltage needs to be held to within what error, so any value is within spec.
  2. Break the connection between the collector of Q2 and the base of Q1. It makes no sense.
  3. Increase R2. You didn't specify the characteristics of the output, but judging from the 2 kΩ load formed by R3 you should be able to make R2 at least 20 kΩ.
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