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As a PCB manufacturer do we have any fool proof method to check correct layer order? I tried to check the impedance with standard Er, H. It works, but I'm not satisfied with the methodology I followed.

I want to ask the community if you have any measures! I want the methodology check to be independent of the customer provided stack up drawing or information.

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    \$\begingroup\$ The only "correct" stackup is the one desired by the customer. Make sure you make it easy for them to document it adequately for you. Other than that, you need to get the outer layers correct -- you can use pin 1 locations on asymmetric multipin devices to help get that right -- but unless you're doing blind/buried vias, most permutations of the inner layers will be functionally equivalent. \$\endgroup\$ – Dave Tweed Jan 9 '13 at 16:12
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    \$\begingroup\$ This is not correct -> "most permutations of the inner layers will be functionally equivalent". There can be many many cases where the inner layers of a PCB stack have to be exactly correct. Routing of critical high speed busses and signals is done with reference to a particular GND plane and the thickness and type of material between those layers determines the impedance of the routing. Multiple GND planes may also be used to isolate one critical signal layer from another too. So layer order can matter a whole lot. (Cont next comment). \$\endgroup\$ – Michael Karas Jan 9 '13 at 16:41
  • \$\begingroup\$ (Cont from prev comment) In today's world where high speed dense boards have PCIe, SATA3, 10GbE, QPI, USB3 and other signalling with GHz rates this is more common than you would think. \$\endgroup\$ – Michael Karas Jan 9 '13 at 16:42
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    \$\begingroup\$ @MichaelKaras: The OP already mentioned impedance control; I didn't think I needed to mention it again. My point was that the connectivity will be the same. Furthermore, if the OP was building the kinds of boards you're talking about, he wouldn't be asking the question here; his customers would be making damn sure he was already getting it right. \$\endgroup\$ – Dave Tweed Jan 9 '13 at 16:53
  • \$\begingroup\$ @Tweed - That justification still does not make your comment correct. \$\endgroup\$ – Michael Karas Jan 9 '13 at 16:59
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I am a strong proponent of putting readable layer indicators on each layer that can be seen through the board after it is fabricated. Such markings, when done correctly, can be used to very quickly determine that all layers are in the correct place. Here is an example of how these could look for an 8 layer board. On layers with internal plane fills the plane is cut back away from the layer indicators and the outer solder mask contains an opening on each side over the marker area.

enter image description here

Once the board is all fabricated the layer markers appear as follows and can be easily seen when the blank board is held up in front of a light source.

enter image description here

This scheme also is useful for sorting layers of Gerber films and the best part of it is that it is totally under the design control of the customer.

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    \$\begingroup\$ I'm going to start doing this on my boards from now on. Besides being a good indicator, it just looks cool! I just saw this on a Dave Jones EEVBlog video: i.imgur.com/lehmf.png \$\endgroup\$ – dext0rb Jan 9 '13 at 17:15
  • \$\begingroup\$ How does this actually help? If they are out of order, the layer marker numbers will still appear in order even if the stackup is out of order, right? \$\endgroup\$ – ryantm Mar 26 '14 at 15:56
  • \$\begingroup\$ @ryantm - The layer indicators actually serve multiple purposes. The main one being that they help the PCB fabrication shop identify the masks and the board subassemblies. Multi-layer boards are built up in stages and then laminated together. These markers can help making sure the correct pieces get laminated in the right order. For after the board is built it is easy to look through the board with a strong light behind it and see the marks through the semi-transparent FR4 material. It is easy to tell which layers are deeper into the assembly than others. \$\endgroup\$ – Michael Karas Mar 27 '14 at 5:12
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Taking Michael's feedback a step further, in the area that you use for alignment structures, have your customers place those numbering "tags" beside each board in the waste area. Enforce that they place YOUR structures on the proper layers upon submission. Have them sign off that the count sequence is correct. If you produce boards that count properly and it's still built wrong it's their fault.

This is what's done on the semiconductor side. No one ever gets it wrong and still keeps their job.

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    \$\begingroup\$ Pcb fab is a lot more competitive business than semiconductor foundry. If a fab shop is going to put that kind of demands on me as a customer, they better offer something substantial back in return --- like noticeably lower prices. Otherwise I'll go to one of the hundreds of other shops out there that don't make me jump through hoops like this. \$\endgroup\$ – The Photon Jan 10 '13 at 0:30
  • \$\begingroup\$ "Pcb fab is a lot more competitive business than semiconductor foundry. " proof please. \$\endgroup\$ – placeholder Jan 10 '13 at 0:32
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    \$\begingroup\$ How many foundry vendors are there out there? How many pcb fabs are there? My point is, PCB fabs don't have the leverage with their customer to tell their customer how to design their boards --- and your answer implies that chip foundries do. That there is proof that PCB fabs have to compete harder to get their customers. \$\endgroup\$ – The Photon Jan 10 '13 at 0:35
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In general the layers should be labeled in the gerber files. And the assembly drawing should show the stackup. If the gerber layers aren't clear (e.g. GND instead of LAYER1), then look at the stackup.

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http://www.speedingedge.com/PDF-Files/Test%20Structures.pdf

Another neat trick you can do is build vertical copper lines on perpendicular sides of your board. This will confirm none of the layers were shifted in the X-Y plane before being laminated.

Of course if you're using a high end fab, this is almost always a non-issue. But its something useful for those using cheaper fab solutions.

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