# XILINX Vivado VHDL using "printf"

In the C programming language, you can use printf to print out (for example) variables in the console window. I am using Vivado right now and programming with VHDL. I have some registers I want to read. Is there an easy way, like printf, to show me the data the registers are holding?

I don't want to use simulation, because the registers get written to from an external component.

• Did you look into "report" statement in VHDL? Nov 30 '20 at 17:27
• Since the hardware works in parallel, how often would/should the printf execute? I think simulation is needed.
– AJN
Nov 30 '20 at 17:31
• @MituRaj thank you. I looked into it and I found this report "The value of 'a' is " & integer'image(RST); How can I do the same with a STD_LOGIC or STD_LOGIC_VECTOR? Nov 30 '20 at 17:33
• @AJN I just want to read the first few and last few adresses of a ram. Nov 30 '20 at 17:34
• @MituRaj idk. I am using XILINX Vivado 2020. The simulation doesn't help. I am writing from an ADC to a RAM and would like to know the values the RAM holds after it gets written Nov 30 '20 at 17:43

You can use the Vivado Chipscope debug core to view registers at run-time on your device.

Here are the steps to get that working.

1. In your source files add mark_debug attributes to the signals you want to debug.

attribute mark_debug : string;
attribute mark_debug of some_signal_name : signal is "true";
attribute mark_debug of some_other_signal : signal is "true";

2. In the project manager select "SYNTHESIS -> Set Up Debug". Synthesis will then run and the debug wizard will open. It will automatically try to add the signals you marked in the prior step.

3. After you complete the wizard, with your synthesized design still open, click the save icon in the upper left on the tool bar. This will write your debug constraints to one of your constraints files.

4. Generate your bit-stream. Then program your device with the bit-stream over JTAG. Make sure to specify your LTX file when programming. The LTX file should generate in the same folder as your bit-stream. Once you program the device you should see a debug window that shows your signals.

For more information see Xilinx user guide UG908 Programming and Debugging.

Also see the Vivado 2020.1 - Programming and Debug page.

• Thanks for your insights. I will look into it Nov 30 '20 at 20:50

"printf" and similar statements can only be used in simulation, not in synthesis.

FPGA vendors do however provide tools for on-chip debugging. I have used Altera's signaltap extensively and found it invaluable. I belive the Xilinx counterpart is chipscope but I have not used it myself.

• Indeed. The other choice is to give the design itself some sort of output, but that's typically more sensible when it's a functional rather than purely debug goal. Nov 30 '20 at 19:28

Realistically, this is best done in simulation; using Assert and/or Report. But you need to simulate the ADC too. Some manufacturers like Analog Devices supply VHDL simulation models of their ADCs and even cores to interface with them : others don't.

Worst case, you might have to write a simulation model of the ADC, from the specifications and timings in its datasheet. This has the benefit that you can thoroughly test your interface to it in simulation before getting to the hardware stage.

In real hardware you're looking at instantiating a Chipscope ILA core and connecting to it through the JTAG interface to examine registers : to read RAM you'd need to persuade your hardware to transfer its contents onto signals connected to Chipscope.

Alternatively, use an FPGA with an embedded ARM processor (Zynq-7 series, or Ultrascale for example). Map that RAM onto the AXI bus to make it accessible to the ARM CPU. Then read the addresses it's mapped to, in a C program running on the ARM, and display the results using ... printf.