Realistically, this is best done in simulation; using Assert and/or Report. But you need to simulate the ADC too. Some manufacturers like Analog Devices supply VHDL simulation models of their ADCs and even cores to interface with them : others don't.
Worst case, you might have to write a simulation model of the ADC, from the specifications and timings in its datasheet. This has the benefit that you can thoroughly test your interface to it in simulation before getting to the hardware stage.
In real hardware you're looking at instantiating a Chipscope ILA core and connecting to it through the JTAG interface to examine registers : to read RAM you'd need to persuade your hardware to transfer its contents onto signals connected to Chipscope.
Alternatively, use an FPGA with an embedded ARM processor (Zynq-7 series, or Ultrascale for example). Map that RAM onto the AXI bus to make it accessible to the ARM CPU. Then read the addresses it's mapped to, in a C program running on the ARM, and display the results using ... printf.