What's the best way to debounce a slider switch?

Question

I'm really struggling with a VHDL implementation of a debouncing circuit for 2-position slider switches.I had initially planned to use an SR latch to do this but couldn't figure out how to make it work. (I'm using a Basys 3 board with Artix-7 FPGA).

I believe the problem is the way that the switches are connected to the FPGA. I found this video to be very helpful in explaining the SR latch, but he has an active low SPDT switch with two outputs. My switches appear to be connected the opposite way round, as shown in the image below which is from the Basys 3 datasheet.

One switch position is powered, and the other is grounded. Then there's a single output to the FPGA. Firstly, if this kind of switch has a particular name, can someone tell me what that is? I assumed these were SPDT switches but this configuration makes me think they're not, and I also don't know what the arrows on the switches indicate? Does it mean that the default position is grounded?

Either way, since the switch doesn't have 2 outputs to the FPGA, using an SR latch doesn't seem viable as it requires two inputs - one for each NAND gate.

Can anyone provide some info on these switches so I can research some more, since I don't seem to be able to find any info about this configuration, and the datasheet doesn't provide any info except this image. And if possible, can you suggest a method to debounce a switch like this, either in VHDL or hardware(a circuit at the switch output, not a change to the existing hardware)?

Edit: one method I've tried is using a counter which allows 10ms for the input to settle. If the input changes due to switch bounce, it will restart this counter. This works, but it means that there's a delay which I'm worried will cause timing issues. As you can see in the simulation below (which has simulated bounces for 10ms), the debounced output is unbounded until about 20ms, because it has counted 10ms after the final rising edge of the bounces. I'd prefer a method which works more like the SR latch, where it latches the input straight away. Is this possible?

Answer 1

I don't know the details of your application, but adding a capacitor to ground between the spdt switch and the resistor will quelch contact bounce. If the switch bounces while connecting or disconnecting to the high rail, the capacitor will hold a charge during that bounce, and similarly when the switch is connecting or disconnecting to ground. The capacitance required depends upon how much current your circuit draws from the switch, and how long it is possible for the switch to bounce.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 2

You really have two issues to deal with here. First, you need to deal with metastability. To do that, you'd typically connect up an inverter to one of the inputs of your SR flip flop (creating a D flip flop), so you can drive both the inputs to your SR from your single switch:

^{simulate this circuit – Schematic created using CircuitLab}

Then you normally want to run that signal through another flip flop to synchronize it with the clock on the rest of your system.

^{simulate this circuit}

Just to be clear, both of those will be clocked with your system clock.

After that, you do your debouncing. Typically, you do this with a counter that starts running when you see (say) a high signal, and resets when you see a low signal. Then you produce an output when (and only when) the counter reaches some upper limit (long enough to cover bouncing).

I've never actually tried to implement it, but I think you could probably sort of reverse the order of those things if you wanted. Instead of sampling and then counting down to cover switch bounces, you could probably do a count on your clock to produce a clock for the flip flops with a very low duty cycle. For example, if you're using a 10 MHz clock for the rest of the system, feed the flip flops with a clock that has one high pulse every 50 ms, so it samples the signal from the switch for .1 uS every 50 ms.

It seems like this could have at least some advantage with an FPGA, by allowing you to do more of the work with dedicated clock management resources, and reserve the fabric for your other logic.

But as I said, I've never actually tried that, so I wouldn't call this a recommendation, just a thought you might find interesting.

Answer 3

From reading through the comments, I think that you need to rephrase your question to "What's the best way to debounce multiple slider switches?" especially pertaining to the comments by Chris Stratton about intermediate values.

Intermediate values will be generated when changing two or more sliders at the same time, i.e. to the human brain it appears to be almost simultaneous, but to your FPGA running at 100 MHz, many clock cycles will occur between the slider changes.

For that you will need a bus debouncer that treats the multiple switch positions as a single value where any change on any slider will reset the common debouncer counter.

Bus Debouncer

This debouncer assumes its inputs are synchronised to the clock.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Debounce is
    generic
    (
        CLOCK_PERIOD   : time := 10 ns;
        DEBOUNCE_PERIOD: time := 100 ms;  -- Rule of thumb for a slider switch.
        BUS_WIDTH      : positive := 16
    );
    port
    (
        clock : in std_logic;
        input : in std_logic_vector(BUS_WIDTH - 1 downto 0);                      -- Synchronous but noisy input.
        output: out std_logic_vector(BUS_WIDTH - 1 downto 0) := (others => '0');  -- Debounced and filtered output.
        change: out std_logic := '0'                                              -- Goes high for 1 clock cycle when debounced.
    );
end entity;

architecture V1 of Debounce is

    constant MAX_COUNT: natural := DEBOUNCE_PERIOD / CLOCK_PERIOD - 1;
    signal counter: natural range 0 to MAX_COUNT := 0;  -- Specify the range to reduce number of bits that are synthesised.

begin

    process(all)
        variable v_change: boolean := false;
    begin
        if rising_edge(clock) then
            counter <= 0;   -- Freeze the counter by default to reduce switching losses when input equals output.
            change <= '0';

            if counter >= MAX_COUNT then    -- If successfully debounced, notify what happened.
                output <= input;
                change <= '1';
            elsif v_change then             -- Hysteresis.
                counter <= counter + 1;         -- Only increment when input and output differ.
            end if;
        end if;

        -- Change detection compares the input bus with the output bus and flags any discrepancy.
        v_change := input /= output;
    end process;

end architecture;

Synchroniser

You also need a bus sychroniser to synchronise all the slider switch inputs to the clock before feeding them to the debouncer.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Sync is
    generic
    (
        SYNC_BITS: positive := 3;  -- Number of bits in the synchronisation buffer (2 minimum).
        BUS_WIDTH: positive := 16
    );
    port
    (
        clock : in std_logic;
        input : in std_logic_vector(BUS_WIDTH - 1 downto 0);  -- Asynchronous input.
        output: out std_logic_vector(BUS_WIDTH - 1 downto 0)  -- Synchronous output.
    );
end entity;

architecture V1 of Sync is

    constant SYNC_BUFFER_MSB: positive := SYNC_BITS - 1;
    subtype TSyncBuffer is std_logic_vector(SYNC_BUFFER_MSB downto 0);
    type TSyncBuffers is array(0 to BUS_WIDTH - 1) of TSyncBuffer;
    signal sync_buffers: TSyncBuffers;

begin

    assert SYNC_BITS >= 2 report "Need a minimum of 2 bits in the synchronisation buffer.";

    process(all)
    begin
        if rising_edge(clock) then
            for i in 0 to BUS_WIDTH - 1 loop
                sync_buffers(i) <= sync_buffers(i)(SYNC_BUFFER_MSB - 1 downto 0) & input(i);
            end loop;
        end if;
        for i in 0 to BUS_WIDTH - 1 loop
            output(i) <= sync_buffers(i)(SYNC_BUFFER_MSB);
        end loop;
    end process;

end architecture;