Q and Q' does not have a value yet, then how does the circuit proceed?
That is correct. There is no way to know how the circuit would proceed.
To fix this we can use an asynchronous or synchronous RESET or PRESET input to set the output to a known state. An asynchronous input does not depend on the clock, but a synchronous input depends on the clock.
Here is a reference circuit for a Master-Slave JK Flip-Flop with asynchronous reset and set inputs.
JK Flip-Flop with Asynchronous RESET and SET input
simulate this circuit - Schematic created using MultisimLive
This is the circuit of a JK Flip-Flop with an asynchronous RESET and PRESET. A HIGH on an asynchronous RESET input sets Q to
LOW and Q' to
HIGH, and this operation is independent of the clock. Similarly, a
HIGH on an asynchronous PRESET input sets Q to
HIGH and Q' to
When the RESET input is
HIGH, the output of the NOT gate (U11) will be
LOW. The output of the NAND gate (U12) will become
HIGH since one of the inputs is
LOW. This will make the output of the NAND gate (U13) Q to be set to
LOW. Similarly, other cases can be analysed, and is left as an exercise to the reader.
Behaviour is not defined for the case when both PRESET and RESET are
HIGH, since it is not allowed (and meaningless).
The section 2 of this paper by Clifford Cummings, Don Mills and Steve Golson is particularly relevant, so I'm quoting it here
For individual ASICs, the primary purpose of a reset is to force the ASIC design into a known state for simulation. Once the ASIC is built, the
need for the ASIC to have reset applied is determined by the system, the application of the ASIC,
and the design of the ASIC. For instance, many data path communication ASICs are designed to
synchronize to an input data stream, process the data, and then output it. If sync is ever lost, the
ASIC goes through a routine to re-acquire sync. If this type of ASIC is designed correctly, such
that all unused states point to the “start acquiring sync” state, it can function properly in a system
without ever being reset. A system reset would be required on power up for such an ASIC if the
state machines in the ASIC took advantage of “don’t care” logic reduction during the synthesis
We believe that, in general, every flip-flop in an ASIC should be resetable whether or not it is
required by the system. In some cases, when pipelined flip-flops (shift register flip-flops) are
used in high speed applications, reset might be eliminated from some flip-flops to achieve higher
performance designs. This type of environment requires a predetermined number of clocks
during the reset active period to put the ASIC into a known state.
ASIC: Application Specific Integrated Circuit