# Difference between Gate Instantiation and SystemVerilog operator

Today I learned about & and ! operators. But I can't understand what is the difference between these two:

1. A=B & C;

2. AND(A,B,C);

Do they have exactly the same usage?

There are actually different concepts. When you use AND gate it means that you have two ( or more) "one bit" inputs and the output is zero unless all of them are high. On the other hand the operator "&" means bitwise "and". It means that if you have two ,let's say, four bits binary numbers "a" and "b", "a & b" will be also a four bit binary number,in which each bit is the result of and operation on respective bits. For example :

A = 4'b1001

B = 4'b1110

then :

A & B = 4'b1000


If you want to use & instead of AND gate you have to remember that you have to assign the value to it:

assign out = a & b

above line is equal to:

AND(out,a,b);


Conclusion: as far as we are working with one bit inputs, it doesn't make difference but we have to remember that the concepts are different.

*By the way for the above example if you use &A the result will be 0. It actually ands all of the bits in A. These kind of operators are called Reduction operators. So & operator has two usages:

1. Reduction operator : ands all of the bits
2. Bitwise operator : ands the bits of two different input respectively and returns the result.

We can model these two usages with AND gate:

For example A =4'b1010

&A = AND (out,A[0],A[1],A[2],A[3])