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We are looking at PIC24FJ256GA705 here. It is connected to an FPGA and the FPGA must transfer a few kB of data as fast as possible. I assume that parallel transfer is the best option here, parallel transfer of 16-bits at a time. Some handshake signals must be worked out here since the PIC and FPGA operate in unrelated clock domains.

Lets assume a simple operation where the PIC reads the two 8-bit words and then stores it in RAM. The PIC is operating at 32MHz. How many clock cycles will this simple operation take? I think this is a 16-bit PIC which means that this reading should be possible in a single instruction actually. I want to then also consider the hand-shake signals and see what is the maximum data rate that can be achieved.

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    \$\begingroup\$ Note that you should be able to translate the clock domain inside the FPGA \$\endgroup\$ Commented Dec 2, 2020 at 16:19
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    \$\begingroup\$ Wide parallel inputs into modern MCUs are an extremely rare design decision, fast serial interfaces or at least narrow parallel ones supported by DMA would be more typical. This sounds a bit like an XY problem where you may need to refactor the task division between the MCU and FPGA. But with what you've proposed, the speed is really something for you to research yourself. \$\endgroup\$ Commented Dec 2, 2020 at 16:23
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    \$\begingroup\$ Your PIC should be supporting SPI @> 12 MHz. Did you consider using that? \$\endgroup\$
    – Mitu Raj
    Commented Dec 2, 2020 at 16:35
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    \$\begingroup\$ "As fast as possible" is meaningless. There's got to be some maximum transfer time above which your system is just broken and there's no point, and some minimum below which no advantage is gained. So -- what's that range, and how many bits exactly? \$\endgroup\$
    – TimWescott
    Commented Dec 2, 2020 at 17:12
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    \$\begingroup\$ In terms of power, you can suspend most of the FPGA and leave just a simple state machine to transfer data out of the block RAM. Remember, the power consumption of modern logic is heavily dominated by dynamic change, if it's not going kerchunk every clock it's not drawing much. Typically an MCU is faster as the timing master since the software can dictate rather than respond. \$\endgroup\$ Commented Dec 2, 2020 at 23:34

2 Answers 2

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The PIC24FJ256GA705 data sheet lists a couple of FIFO modes in addition to SPI and I2S. Maybe that is what you’re looking for.

Deal with the clock domain conversion in the FPGA.

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I suggest you look at using the PIC24F DMA controller to transfer SPI data directly into RAM.

You'll have to read the datasheet to figure out what data rates are possible.

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