# Using strategic sampling noise to increase sampling resolution

Dithering is used to add virtual resolution to an oversampling ADC, and for instance this discussion involves some of the math involved, and the criteria.

Take for instance an Arduino with 10 bit sampling. The unit has is the ability to set a digital pin to a random value, or a PWM output to a random value. It also has the ability to define a different Vref for ADC conversions. Would a simple circuit that drove the Vref with a filtered random digital signal between 5V and 1 LSB below 5V be a good solution for low-cost dithering?

The thought is that if the Vref were being altered, then the oversampling benefit would be available on all channels, not just one at a time. I can see there will be an over-read of the raw voltage of 0.5 LSB to be corrected for but this is a simple operation.

(I would add a schematic but the plugin seems to not work at present)

Altering Vref would be a multiplicative scaling, that's not really going to be useful across the range of inputs in walking values across code thresholds a statistical fraction of the time as dithering attempts to do.

For dithering you want additive noise, not multiplicative distortion that is functionally gain variation.

Eg, you want to add various fractions of an LSB so that sometimes you hit the higher of the closest two codes and sometimes the lower, and then if you analyze the comparative rate of the two and assume your noise is random, you can over time calculate a more precise intermediate value to a fraction of an LSB.

In contrast, dithering by gain variation would only really work usefully for a small range of inputs, in the upper part of the allowable input range, lower in the input range the effect would be proportinoally reduced.

• It took me a little too long to see what you were meaning, but I see it now and you're dead right. Perhaps then an incoming signal needs to be divided against the random pin and then sampled. This would cause a narrowing of the sample to 0 + 0.5 LSB and 5 - 0.5 LSB, to be corrected for. Would you agree? – J Collins Dec 3 '20 at 14:01
• No, division won't work either. It needs to be additive, not division/multiplication/scaling – Chris Stratton Dec 3 '20 at 14:07
• God you're right, how frustrating..! Need to be able to move the lower and higher voltage references then.. – J Collins Dec 3 '20 at 14:47
• You're trying too hard. Just buy a better ADC or an MCU with a better one. – Chris Stratton Dec 3 '20 at 14:55
• Yes changing the ground reference is impossible so the idea isn't going to work, additive is the only way. – J Collins Dec 3 '20 at 15:50

No, while it could work on DC, the capacitors would shunt the PWM output directly. However Atmel/Microchip has an application note AVR121 which explains use of dither.

• Indeed, the lower capacitor should be to ground, that may be a drafting error. But noise applied to Vref is effective only in proportion to where the signal falls in the input range. Atmel's examples with Vref noise seem to use signals comparable to Vref which is a special, limited case. – Chris Stratton Dec 2 '20 at 18:20