This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is basically known?
I am using a Terasic DE10 Lite board, mirroring video from a Mac SE/30 (512x342x1bpp) on a VGA display. Mac connections are vsync, hsync and pixel from the analog board, level converted to 3.3V and then connected to FPGA board GPIOs. At 1024x768 it’s a fairly good fit if pixel doubled. Getting VGA out at 60Hz is not hard, an ALTPLL IP block at 65Mhz makes it just a matter of counting front/back porch and sync pulses.
Copying the Mac signal is a little harder. I ended up with one @always on an ALTPLL clock running at 15.67 MHz (and experiemented with mult/div numbers to try to get it as close as possible), the Mac’s pixel output rate. I cannot exactly match the clock rate this way. This counts down the vertical blank period then for each line counts in until pixels begin and samples each pixel. Pixels are written to a slab of dual port RAM made from another IP block and output by the VGA routine.
This works and is perfectly readable. But it is ugly since there are sampling errors due to the slightly mismatched clocks. If instead of the ALTPLL clock I take CPUCLK from the Mac's PDS connector and use that to clock in the pixels, everything is as steady as can be. Using the FPGA clock the pixels are unsteady and randomly change where they should not.
The question is, what do you do if you can’t take the system clock? I think there must be some way to dynamically adjust frequency and phase shift based on input but I don’t know where to look.
(this question got no response at Stack Overflow, is perhaps a better fit here)