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I was using the following code for a multiplexing circuit to activate 7 seg display on the Basys 3 FPGA. As for multiplexing circuit you don't often need to press a reset, so I was just wondering What happens if we don't press reset for long time here? I believe the value of all 18 bits will be 111......1, and if that is the case, how would fpga reset the counting. Will it just get stuck at 111...1? or will it start replacing bits from LSB/MSB to keep the counter on?

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    \$\begingroup\$ count will wrap back to zero, exactly what would happen if it could toggle a bit 18 if it existed \$\endgroup\$
    – johnnymopo
    Dec 3, 2020 at 0:12

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No. It will not get stuck or so. The final increment will be \$111... \rightarrow 000... \$ , as the carry bit gets truncated. Thus the counter wraps back and starts counting again from 000 ...

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Most FPGA is designed in a way to increment and then reset on overflow to avoid blocking of hardware leading to generating an error. The counting register used to store the value is of fixed bit, once it reaches all 1, it resets itself and starts again from 0. We may use register pair for longer duration counting, in which two registers are used to store parts of the counter.

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