# Designing a down counter using Xilinx ISE design

We are trying to design a circuit that counts down from 9.99 to 0.00. Could you give us some tips?

• At which level do you want to write your HDL code? For me, it'll be easier to decrement from 999, and then place a fixed point . at the output stage. – Light Dec 3 '20 at 6:04
• we arent using vhdl. we are using schematic design. – electro Dec 3 '20 at 6:36
• Please edit your question to give all the information that's needed to provide you with a useful answer. – The Photon Dec 3 '20 at 6:40