# Gate signal problem on my flyback

Here is my flyback converter design.

Vin: 110V
Vout: 24V
Iout: 1A (max)
Desired efficiency: 85%
Transformer ->
P1: 6T
S1: 6T
S2: 5T (aux)
Vro: 24V
EFD30
I determined 15uH for Lp
Ls1: 15uH and Ls2: 8uH
SMPS IC: NCP1252-A (max duty cycle: 48%) datasheet
Mosfet: STP75NF20 datasheet

When the transformer is not connected at the circuit, PWM signal at the mosfet gate is CLEAR and PROPER.
But, the transformer is connected at the circuit, gate signal form is being broken.

I thougth that the SMPS IC could not be able to generate the gate signal when directly connected with mosfet. So, I used a mosfet driver. But, the result is the same. Frustration! So, my efficiency remains low (25%)

Why is the gate signal being broken?

I measured leakage inductance as 5uH. Does the leakage inductance cause a problem about PWM?

• The gate signal looks OK so, what is your actual problem. I mean you could look at any signal and get too picky about this nuance or that nuance but, is there something actually wrong with your design that makes it not work correctly? What peak current flows through your flyback transformer primary? I estimate 13 amps. Dec 3 '20 at 13:16
• The IC can source 500mA and sink 800mA on the gate drive, and was characterized with 1nF capacitance (rise and fall times of 28ns and 22ns). You are operating at close to 500kHz, so my guess is that the drive current is insufficient for your application - in this case a discrete driver with higher sink/source capability is the right solution. Dec 3 '20 at 13:30
• Is the current through the transformer and MOSFET what you think it needs to be? The current should be easy to measure as you have sense resistors. Dec 3 '20 at 13:44
• Possible scope probing problem - you have to be very careful when probing with high currents. Use a spring clip and a very local ground pin. Dec 3 '20 at 14:36
• Have you ever heard of Miller plateau? I can only suggest to have a look to any MOSFET driving application note. Dec 3 '20 at 18:29

I don't have any answers about distorted gate drive signals but I'll list down a few mistakes I see:

• For $$\\mathrm{P_{OUT} = 24W}\$$ and $$\\mathrm{f_{SW} = 500kHz}\$$, the primary inductance will be much higher than $$\\mathrm{15\mu H}\$$ even for DCM. Nevertheless, let's see what that $$\\mathrm{15\mu H}\$$ causes:

• If you force the converter to output 24 Watts then the controller chip will increase the on-time to maintain the required energy which will be stored by the primary inductance (its magnetic field, actually) then transferred to secondary (Remember $$\\mathrm{V_{IN} = L_p\ i_{ppk}/t_{on}}\$$, and $$\\mathrm{E_p=0.5\ L_p\ i_{ppk}^2}\$$), but the duty cycle is limited to ~%48 by the controller chip, as seen in the oscillogram.

• For $$\\mathrm{L_p = 15\mu H}\$$ and $$\\mathrm{t_{on} = 1\mu s}\$$ (i.e. limited duty-cycle), the peak current will be ~7.3A and the RMS current will be 3A. That's why you see ~1A input current at 110VDC input.

So, maybe the distortion is caused by the duty-cycle limitation. Increase the primary inductance to something around $$\\mathrm{100-120\mu H}\$$ and see what happens.

NOTE: The transformer of a flyback converter must have an air gap because most of the energy is stored by the gap itself.

By the way, since you didn't share the full schematic, I'm assuming that the loop is properly closed.

PS: Say hello to Oguz Bey and Selman Bey for me :)

• I will implement your suggestion and write the result here. Aleykum selam :) Dec 3 '20 at 17:57
• @BunyaminTAMAR From one of your comments above: Also, another application in our devices uses 125 kHz and same mosfet. No problem at that app. But, topology is different and forward. Probably it's the 72-to-24 150W railway converter that I designed when I was working there. Now if your aim is to design an alternative converter for railway then do not ever use flyback topology. The converter will not pass the railway EMC tests, I assure you. Dec 4 '20 at 4:27
• I guess that: The energy stored in ton time is transferred in toff time, so the EMC problem occurs. Since there is an instant transfer in the forward topology, there is no problem. Is it true? Dec 4 '20 at 5:13
• @BunyaminTAMAR no, not exactly. There are other things, and they are all out of context here. Just take the statement above as a recommendation. Dec 4 '20 at 5:42
• Now if your aim is to design an alternative converter for railway then do not ever use flyback topology. The converter will not pass the railway EMC tests, I assure you. but still I have to solve this problem Dec 4 '20 at 6:59