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Essentially, in our electronics textbook Microelectronics by Sedra/Smith, when beginning to discuss IC amplifier design, the topic of active loading comes up before cascoding. Throughout the text, for example, when using an NMOS common source amplifier, it will be biased by an active load PMOS, but the reason for this is never explained. When researching myself, it seems that it doesn’t really matter, as you can always adjust voltages to make a device work, but I must be missing something.

Why is it so ubiquitous to see a PMOS active load in an NMOS common source amp?

I’m assuming it has something to do with the positive power rail and avoiding gain being too high from cascoding, but maybe I’m way off base.enter image description here

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In our common-source amplifier, a primary goal of our active load is to provide a high small-signal impedance (translating to a high gain) while having only a modest large-signal voltage drop across it at the operating point (also called quiescent point in some texts).

In order to achieve this, we can use a MOSFET configured for nearly constant current, i.e. a MOSFET configured as the output side of a current mirror (or a constant Vgs in a simplified design/analysis).

The complication is that the MOSFET that we fabricate is a nearly symmetric device (and in some models such as the tsmc18 which I am familiar with, fully-symmetric); the source is always the side of the channel with lower voltage for NMOS, and higher voltage for a PMOS.

Compare these two topologies:

enter image description here enter image description here

Notice which side ends up being the source (marked with the arrow). In the first topology (PMOS), the higher voltage is the source, and that's the rail. Perfect, because it means that our constant bias voltage \$V_{bp}\$ creates a nearly constant current through the drain, and the impedance seen looking into that drain is very high (it's the output impedance associated with channel-length modulation).

Now look at the second topology. The top FET is an nFET, meaning that its source is tied to the output. The impedance seen looking into the source is very low, because Vgs varies significantly as the amplifier's output voltage (i.e. the top FET's source voltage) varies. In fact, this active load is actively counterproductive -- it creates a feedback structure that tries to hold Vgs of the two FETs relatively similar to each other because they have the same current running through them. This makes it no longer amplify -- depending on the relative shape ratios of the top and bottom FETs it has a tiny bit of gain at best, or is a really bad buffer, or even attenuates.

Our active load doesn't meet our goals, and our amplifier also fails to meet its goals as a consequence.

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  • \$\begingroup\$ If the top FET is a depletion-mode nFET, configured as a current source, wouldn't the amplifier work? I believe nobody is using depletion-mode FETs in IC design nowadays, so the PMOS solution is preferred. \$\endgroup\$
    – anrieff
    Commented Dec 4, 2020 at 3:54
  • \$\begingroup\$ @anrieff The process I used did not provide depletion-mode FETs, so I'm not familiar with their behavior. I would suspect that it still wouldn't work because the channel still has the same source/drain, just that the band structure in the channel makes for an effectively negative threshold voltage without changing the differential/small-signal behavior. \$\endgroup\$
    – nanofarad
    Commented Dec 4, 2020 at 3:57
  • \$\begingroup\$ In discrete design you'd need to add a resistor downstream of the top FET, and tie its gate to the node after the resistor (which is also the Vout node). Then the Vgs of the two FETs will be different, and of course their effective Vth is different. I think it might work. \$\endgroup\$
    – anrieff
    Commented Dec 4, 2020 at 4:15
  • \$\begingroup\$ @anrieff I suspect that this arrangement gives poor output impedance because of the source voltage varying with the drain current of the bottom FET -- I'd need to think about it more closely with either math or simulation to fully understand it. \$\endgroup\$
    – nanofarad
    Commented Dec 4, 2020 at 4:41
  • \$\begingroup\$ This is a great explanation and exactly what I was looking for, thank you, nanofarad. So the main reasoning is that by using an NMOS as an active load for an NMOS CS amp, we are creating negative feedback by varying the Vgs of the active load NMOS, thus not creating a constant current source? \$\endgroup\$
    – ModularMan
    Commented Dec 4, 2020 at 17:57

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