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After skimming through this article, I am wondering what are the benefits of SWD debugging over JTAG debugging?

I understand SWD uses less wires/pins, takes up less space etc. But how does it play out in terms of performance, features and cost of the hardware programmer/debugger devices? Can code still be break pointed/paused and stepped through in IDE's like Eclipse?

Can an ARM chip be programmed using the SWD interface, like I believe can be done in JTAG?

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  • \$\begingroup\$ ARM based chips with the more recent cores (Cortex, for example) can be programmed and debugged via SWD. \$\endgroup\$ – B Pete Jan 10 '13 at 15:22
  • \$\begingroup\$ @BPete: I've found that with SWD it's hard to debug ST-based chips that use sleep mode; our present boards don't have the pins available for JTAG, but I was wondering if JTAG might be any better in that regard? \$\endgroup\$ – supercat Jan 10 '13 at 16:00
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    \$\begingroup\$ This (SWD) looks a bit like the Spy Bi-Wire interfagce that TI put on a subset of their MSP430 processors. It's a 2-wire JTAG-alike (plus power&ground) with SBWTCLK and SBWTDIO multiplexed on two non-GPIO pins (TEST, and RST/NMI) on an example device. Supported by the EZ430 devkit. And it (SBW) does support stepping and breakpoints! I don't know if TI's own ARMs have the same interface, but it would be interesting if there was enough commonality between them to share programming/debug tools. \$\endgroup\$ – Brian Drummond Jan 11 '13 at 15:33
  • \$\begingroup\$ Your article link is dead, but perhaps this was the article? arm.com/files/pdf/Serial_Wire_Debug.pdf \$\endgroup\$ – Gabriel Staples Feb 8 at 19:31
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SWD should be able to program the ARM chipset plus you can debug and add breakpoints. The other good thing about SWD is you can use the serial wire viewer for your printf statements for debugging. I have only used it with the Keil compiler.

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Electrically

  • Pin Count
    • JTAG requires 4 signal lines
    • SWD only requires 2 signal lines
    • 2-wire JTAG interface specified in IEEE 1149.7 drops the pin count but doesn't seem to be widely available on many ICs. It also reduces bandwidth.
  • Topology
    • JTAG uses a daisy chain configuration for its data lines between chips. JTAG's speed is thus limited by the slowest chip on the chain. Its reset and clear lines are bused (not chained) however which allows for interoperability via SWDJ-DP (see discussion below).
    • 2-wire JTAG allows for a star topology, but it is not used often.
    • SWD allows for star topologies

Functionally

  • SWD is an ARM specific protocol designed specifically for micro debugging.
  • JTAG (Joint Test Action Group) was designed largely for chip and board testing. It is used for boundary scans, checking faults in chips/boards in production. Debugging and flashing micros was an evolution in its application over time.
  • JTAG is in use for multiple microcontroller/processor architectures aside from ARM.

General Discussion

JTAG is more widely supported, as of 2017, by non-ARM micros, programmers and production lines. Programmers for JTAG can be had for cheap in the form of FT232H[*] breakouts and other such programming devices. However, SWD has a distinct advantage in speed and other areas in debugging ARM chips.

Due to the split in the purposed nature of JTAG in testing and SWD in debugging, ARM provides SWJ-DP (serial wire/jtag debug port) via its CoreSight technology which maps SWD pins onto JTAG's clock and reset lines. SWJ-DP therefore allows using both protocols on the same physical connection though not necessarily at the same time or with the same programmers as JTAG and SWD would have to be multiplexed in time.

Useful References

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I may be a bit too late for OP, but maybe it will be useful for some other people with the same question. So, here we go (personal experience): It is possible to program and debug (fetch memory/register maps, break, run from specific point, etc.) with SWD. Using Eclipse here with GDB via J-Link EDU, which goes for ~50 Euros. There are some bugs (resetting target via debugger, sometimes won't connect or fetch maps), but it's relatively cheap and usable, once you get acquainted with it's quirks

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Old question, but none of the answers address the performance comparison. Although the feature set between SWD and JTAG (when using a CoreSight DAP) are near enough the same, SWD sequences are roughly 10% shorter than the equivalent JTAG sequences.

There is no loss in data bandwidth in most cases (particularly streaming reads or writes where bandwidth is most important).

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