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So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.

The general setup of what I'm trying to do.

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    \$\begingroup\$ You'll have to define "doesn't seem to work". Does the Q output store what's on D when you put a rising edge on the clock input (>)? Does Q hold that value at other times when you leave CLK, PRE, CLR alone? Is there a good source of power to the FF during all this? \$\endgroup\$
    – user16324
    Commented Dec 5, 2020 at 14:22
  • \$\begingroup\$ A D-flop doesn't use an enable input, it uses a clock input. \$\endgroup\$
    – Neil_UK
    Commented Dec 5, 2020 at 14:38
  • \$\begingroup\$ so it seems like this setup ignores the conditional. Does the clock input have to be from an actual clock? Could I instead give it something that comes from combinatorial logic? Or to add a conditional, should I AND it with the output of the clock and feed its output to the clock pin. \$\endgroup\$
    – NaiveCoder
    Commented Dec 5, 2020 at 14:54

1 Answer 1

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Examine the internal logic diagram of 7474 D FlipFlop.

Ou will see 2 cascaded latches (NAND gates with feedback).

The data input affects the first (leftmost) FF.

WHen the clock transitions to be high, the logic state of the first crossed_NAND latch is transferred into the 2nd latch.

This rate of transfer has limitations, because of propagation delays of these various NAND gates.

Examine that logic diagram.

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  • \$\begingroup\$ Yeah I figured it out! Thank you so much for your help!!!! \$\endgroup\$
    – NaiveCoder
    Commented Dec 5, 2020 at 15:35

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