Why my register file operates abnormally

Question

I tried to implement a 32x32 bit register file using Logisim, however once I have finished drawing and proceeded to test it by initializing the content of individuals registers to zero using the reset input, only some of them have reset, others have generated an error.

To clarify I have implemented all the sub-circuits used myself and have tested them individually and they work as required.

So, this is the register file and as you can see some outputs are red:

Each register is implemented in a sub-circuit composed of 32 flip flops D (as in the image shown here). The supercircuit error is actually caused by errors in one (or more) of the flip flops that make up the register

Going even deeper, analyzing the flip flops that give errors and the relative latches that compose them, the result is the following: (Note that the clock is enabled although not visible in the screenshots as I am debugging)

I can't explain why some registers and their sub-circuits work correctly while others give this kind of error. I don't think the error is related to my implementation but I'm not sure if the error depends on Logisim itself (I know it has several bugs and issues).

Any additional information or help is welcome as I personally have not found anything about it by searching the web.

Answer 1

Allora, the one suspicious element I see are the two D flops in series that implement your FF compoent. As you stated, these are actually latches. (The “>” symbol on the inputs is misleading – that denotes an edge-sensitive clock. Should probably use “G” to denote a gated latch.) So with the two D latches there is a race condition: rising CLK causes 1st Q to change, but also causes falling clk (gate) to 2nd latch, which latches output. So 2nd latch’s D and G are changing at essentially the same time. Non si fa cosi.

If the simulation is using post-layout timing, then it could be that only some paths fail because their internal routing delays resulted in setup/hold violations at the second latch.