# Trouble designing compensation network for TEC Controller using Analog ADN8831

I am designing a circuit to control a TEC using Analog's ADN8831 as the TEC Controller chip. My application requires more TEC current than the ADN8831 eval board can supply so I built a test board to experiment with.

The ADN8831 offers two amplifiers. The first is used to normalize the NTC to produce a linear voltage with temperature. This is working fine for me. The second amplifier is used to take the set temp and diff it with the NTC temp to produce a control voltage for the TEC MOSFET driver. This is also working fine for me -- when the set and read temperatures match, the ADN8831 temperature lock line is signaled. The TEC heats and cools appropriately.

But here's my issue. According to the Datasheet, the equation for the output of the second op amp is:

$$Vout2 = Vtempset - \frac{Z2}{Z1}(Vout1 - Vtempset)$$

Where Vout1 is the output of the first op-amp, Z1 is the impedance between Vout1 and the second op-amp's negating input and Z2 is the negative feedback for op-amp 2.

Note that when the the set point is reached the output of the second op amp should be Vtempset. I've verified this, and this also triggers the chip to signal its temp lock line.

However, the MOSFET driver uses this voltage range graph:

So the bias on the output is intended to have equilibrium at 1.25v. But I'm seeing that Vout2 matches the equation above, so shortly after I reach temperature lock I lose it because the TEC is still being driven. I've also verified that when I set the setpoint temperature to be 1.25v the TEC does power down when the setpoint is reached. So it works perfectly but only at this temperature.

Vout2 is internally connected to the TEC driver. Neither the data sheet or the eval board have anything special here other than a standard PID network so I'm at a loss how the is supposed to generate the voltages shown in the graph. I've tried a full PID network using default values from the eval board schematic and I've also simplified this down to just a "P" network to better read what's going on. I've also tried simulating several networks in Spice to try to get that elusive 1.25v offset to no avail.

There's got to be something I'm missing and I'm hoping someone here can educate me.

Full schematic of my TEC section here. There is a full PID network in the schematic with values taken from the eval board defaults. I've removed it while I experiment but when present the behavior was the same:

Thanks for looking.