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I want to understand the idea behind using a pull-up resistor.

While looking on the Internet, I came across the following description:

Schematic

By using these two pull-up resistors, one for each input, when switch “A” or “B” is open (OFF), the input is effectively connected to the +5V supply rail via the pull-up resistor. The result is that as there is very little input current into the input of the logic gate, very little voltage is dropped across the pull-up resistor so nearly all the +5V supply voltage is applied to the input pin creating a HIGH, logic “1” condition.

Source: Electronics Tutorials - Pull-up Resistor Application

I assume the same logic is applied to all pull-up resistor applications.

  • Why is there very little input current into the input of a logic gate?
  • What guarantees that?
  • How do I make sure there is only a small voltage drop on the resistor?
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    \$\begingroup\$ Have you looked at a data sheet for the input impedance of a typical gate? It is orders of magnitude above 1 Mohm. \$\endgroup\$
    – Andy aka
    Dec 6, 2020 at 13:34
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    \$\begingroup\$ It needs to be noted that "pull-up resistors" are used in several different situations. The info here only applies to their use on the inputs of a gate or amplifier. \$\endgroup\$
    – Hot Licks
    Dec 7, 2020 at 2:26
  • \$\begingroup\$ There is another important concept with pullup resistors. Sometimes multiple "open collector" or "open drain" outputs are connected together with a single pullup. This avoids contention which would otherwise arise if push-pull outputs were connected together. \$\endgroup\$
    – user57037
    Dec 7, 2020 at 6:58
  • \$\begingroup\$ More than 11 years in, this is surely a duplicate? \$\endgroup\$ Dec 7, 2020 at 9:51
  • \$\begingroup\$ @PeterMortensen, can you clarify what are you exactly asking here? \$\endgroup\$ Dec 8, 2020 at 14:21

1 Answer 1

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As modern chips use CMOS technology, so an input consists primarily of FET gates so virtually no current will flow in or out of a input. Therefore as current is virtually 0, there will be virtually no drop over any resistance.

In practice there can be some leakage currents in the order of 1 to 10 microamperes, so if you use pull-ups with maximum of say 100k it can be pretty sure that there is not too much voltage drop.

The same does not apply to other chip technologies like TTL, as their inputs will sink or source current based on inout voltage. So the pull-ups or pull-downs have to be significantly stronger (lower resistances), and they also use different voltage levels for determining a logic 1 or 0 state.

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  • \$\begingroup\$ That was clear and straightforward. \$\endgroup\$ Dec 6, 2020 at 13:44
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    \$\begingroup\$ "the resistances [...] have to be significantly stronger" sounds off to me. Isn't it more common to say that the pull-ups must be stronger, or the resistances lower? \$\endgroup\$
    – ilkkachu
    Dec 6, 2020 at 23:03
  • \$\begingroup\$ In practice, unless you need to conserve power, 2k2 to 4k7 with everything (except something like H or S TTL) - too high of a pullup resistor value can make an input noise sensitive especially if it is fed by open-collector/tristate outputs.... \$\endgroup\$ Dec 7, 2020 at 2:21
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    \$\begingroup\$ TTL is highly asymmetric, you can get away with a very weak pull up or even no pull-up at all, but if you want to use a pull-down at has to be relatively strong. \$\endgroup\$ Dec 7, 2020 at 5:47
  • \$\begingroup\$ How do you feel about adding something to your answer to do with open-collector outputs? I feel that pullup resistors and open-collector outputs kind of go together. OP didn't really ask about that, but a lot of people find these questions by search engines. \$\endgroup\$
    – user57037
    Dec 7, 2020 at 7:00

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