0
\$\begingroup\$

(Schematic taken from here)

I can't make heads or tails of the push-pull stage similar to the one below - I'd rather try to understand it before this goes to a prototype board.

Q1 will start to conduct as soon as its \$V_{BE}\$ is roughly 0.7V, but how will that happen when its emitter terminal is floating? May I assume Q3 and it's gate capacitance is discharged at the beginning which provides 0V to the node connecting the emitters of Q1 and Q2?

I guess my question is in large part about the circuit's initial conditions and my assumptions about them, but feel free to set me straight.

                          

\$\endgroup\$
2
  • \$\begingroup\$ Remember that Vbe is the voltage BETWEEN the transistor's base and emitter, not the voltage between base and ground. \$\endgroup\$ Dec 6, 2020 at 19:35
  • \$\begingroup\$ @Peter Exactly, and this is the source of my confusion - how can the base of Q1 (or Q2) draw any current, i.e. start to conduct when its emitter is at an undefined potential? So far, all the articles about push-pull configurations I could find don't give a detailed explanation of how and why the BJTs will operate. May I assume that Q1's emitter is at \$0V\$ at t=0? \$\endgroup\$ Dec 7, 2020 at 19:56

1 Answer 1

1
\$\begingroup\$

I think you are right. When a Voltage is applied to the gate of Q1, a current can flow from VCC which will charge the gate capacitor of Q3 which will raise it the gates Voltage to VCC. The time this will take is depending on the value of the parasitic gate capacitance and the gate resistor R2.

Addition: When the PWM signal goes low again, the lower BJT will start conducting pulling the MOSFETs gate to ground by discharging its capacitor.

\$\endgroup\$
2
  • 1
    \$\begingroup\$ It is correct, this is a class B output stage which has the property that if no output current is drawn (when the gate capacitance has been charged) both transistors will be off and no current flows anymore. This happens "automatically". \$\endgroup\$ Dec 6, 2020 at 19:49
  • \$\begingroup\$ "When a Voltage is applied to the gate of Q1, a current can flow from VCC" - how, exactly? As far as I can see, the emitters of both BJTs are initially floating, so how can there ever be a |VBE| of 0,7V? My reasoning with Q3's gate capacitance providing virtual GND was only a guess, too much handwaving for my taste. \$\endgroup\$ Dec 8, 2020 at 1:39

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.